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    Clock generator for CMOS circuits with dynamic registers
    2.
    发明授权
    Clock generator for CMOS circuits with dynamic registers 失效
    具有动态寄存器的CMOS电路的时钟发生器

    公开(公告)号：US06069498A

    公开(公告)日：2000-05-30

    申请号：US945725

    申请日：1997-11-05

    Applicant: Tobias Noll ,  Stefan Meier ,  Matthias Schobinger ,  Erik De Man

    Inventor： Tobias Noll ,  Stefan Meier ,  Matthias Schobinger ,  Erik De Man

    IPC: G06F1/04 ,  G11C7/22 ,  H03K5/151 ,  H03K5/153 ,  H03K5/19 ,  H03K9/06

    CPC classification number: H03K5/153 ,  G11C7/22 ,  H03K5/19

    Abstract: An apparatus has a clock monitoring device, which determines whether or not the clock rate of an input clock signal (.PHI..sub.0) has fallen below a predetermined minimum clock rate. A system is provided which, from the input clock signal, forms a master clock signal (.PHI..sub.m) and a slave clock signal (.PHI..sub.s) which are in a form such that both the switches (S1) of dynamic master registers (ML) and the switches (S2) of dynamic slave registers (SL) are closed provided that the clock rate has fallen below the minimum clock rate. Otherwise, at most either the switches (S1) of the dynamic master latches (ML) or the switches (S2) of the dynamic slave latches (SL) are closed. The primary advantage achieved hereby is that in the event of failure of the input clock signal, in particular in circuits with a high degree of pipelining, undefined register states do not result in an impermissibly high current consumption.

    Abstract translation: PCT No.PCT / DE96 / 00794 Sec。 371日期：1997年11月5日 102（e）日期1997年11月5日PCT提交1996年5月7日PCT公布。 WO96 / 36113 PCT出版物 日期：1996年11月14日装置具有时钟监视装置，其确定输入时钟信号（PHI 0）的时钟速率是否已经低于预定的最小时钟速率。 提供了一种系统，其从输入时钟信号形成主时钟信号（PHI m）和从时钟信号（PHI s），其形式使得动态主机寄存器（ML）的两个开关（S1） 并且动态从属寄存器（SL）的开关（S2）关闭，只要时钟速率已经低于最小时钟速率。 否则，动态从动锁存器（SL）的动态主锁存器（ML）或开关（S2）中的至少一个开关（S1）关闭。 所实现的主要优点是，在输入时钟信号失效的情况下，特别是在具有高流水线流量的电路中，未定义的寄存器状态不会导致不允许的高电流消耗。

    Data converter having a passive filter
    5.
    发明授权
    Data converter having a passive filter 有权
    数据转换器具有无源滤波器

    公开(公告)号：US08018366B2

    公开(公告)日：2011-09-13

    申请号：US12615994

    申请日：2009-11-10

    Applicant: Stephan Henzler ,  Matthias Schobinger ,  Lajos Gazsi

    Inventor： Stephan Henzler ,  Matthias Schobinger ,  Lajos Gazsi

    IPC: H03M1/12

    CPC classification number: H03M1/125 ,  H03M1/504

    Abstract: Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).

    Abstract translation: 公开了电路和系统的示例性实施方式，以及用于信号处理的方法，包括通过无源脉冲调制模数转换器（PMADC）实现的振幅和频带限制信号的采样和量化。

    Method and apparatus for determining an output sequence from an input sequence
    6.
    发明申请
    Method and apparatus for determining an output sequence from an input sequence 有权

    公开(公告)号：US20060198478A1

    公开(公告)日：2006-09-07

    申请号：US11361666

    申请日：2006-02-24

    Applicant: Norbert Neurohr ,  Matthias Schobinger

    Inventor： Norbert Neurohr ,  Matthias Schobinger

    IPC: H04B1/10

    CPC classification number: H04L25/03057 ,  H04L2025/03496

    Abstract: A method and a device for determining an output sequence of output elements from an input sequence of input elements is provided, the method or the device being implemented according to a decision feedback equalizer. The adaptation of coefficients of the equalizer is performed on the basis of an estimated error determined as a function of a scaling (a, c0). According to the invention the scaling (a, c0) is determined such that it differs from a nominal input value by a deviation value during transmission without symbol interference. The deviation value is dependent on non-compensatable inter-symbol interference.

    Processor for comparing picture element blocks (blocks matching processor)
    7.
    发明授权
    Processor for comparing picture element blocks (blocks matching processor) 失效
    用于比较像素块的处理器（块匹配处理器）

    公开(公告)号：US5805239A

    公开(公告)日：1998-09-08

    申请号：US619637

    申请日：1996-03-27

    Applicant: Luc De Vos ,  Matthias Schobinger

    Inventor： Luc De Vos ,  Matthias Schobinger

    IPC: G06T7/20 ,  H04N19/43 ,  H04N19/533 ,  H04N7/36

    CPC classification number: G06T7/202 ,  H04N19/43 ,  H04N19/533

    Abstract: A processor is disclosed, in which a block memory (ADM), a search domain memory (SDM), a two-dimensional processor/memory cell field (PRA) and a control unit (CTRL) are preferably monolithically integrated in a semiconductor chip. The word width of toe search domain memory (SDM) is organised so that the processor/register cell field (PRA) is supplied, in parallel per system cycle (CLK) with data (SF) on picture elements of a new complete column of the search domain. At the same time, a control sequence is stored in the control unit (CTRL). The control sequence supplies data flow control signals (DFC) and addresses (ADR1, ADR2) to the block memory and search domain memory in parallel, per system cycle. The control unit essentially consists of a shift register into which external control signals (CD) of any desired control sequences may be written. An essential advantage of the invention is that it allows a comparatively high hardware utilisation even in the case of block matching algorithms based on an incomplete search.

    Abstract translation: PCT No.PCT / DE94 / 01113 Sec。 371日期：1996年3月27日 102（e）1996年3月27日PCT 1994年9月23日PCT公布。 公开号WO95 / 09404 日期1995年04月6日公开了一种处理器，其中块存储器（ADM），搜索域存储器（SDM），二维处理器/存储单元场（PRA）和控制单元（CTRL）优选地是单片集成 在半导体芯片中。 组织脚趾搜索域内存（SDM）的单词宽度，以便在每个系统周期（CLK）并行提供处理器/寄存器单元字段（PRA），其中数据（SF）在新的完整列的图像元素上 搜索域。 同时，控制序列存储在控制单元（CTRL）中。 每个系统循环，控制顺序将数据流控制信号（DFC）和地址（ADR1，ADR2）并行提供给块存储器和搜索域存储器。 控制单元基本上由移位寄存器组成，可以写入任何所需控制序列的外部控制信号（CD）。 本发明的一个基本优点在于即使在基于不完全搜索的块匹配算法的情况下也允许相对较高的硬件利用率。

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