公开(公告)号：US07655532B1

公开(公告)日：2010-02-02

申请号：US12179892

申请日：2008-07-25

申请人： Neng-Kuo Chen ,  Kuo-Hwa Tzeng ,  Cheng-Yuan Tsai

发明人： Neng-Kuo Chen ,  Kuo-Hwa Tzeng ,  Cheng-Yuan Tsai

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/3125 ,  H01L21/316

摘要： A method of forming a shallow trench isolation region includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; filling a precursor into the opening using spin-on; performing a steam cure to the precursor to generate a dielectric material; after the steam cure, performing a chemical mechanical polish (CMP) to the dielectric material; and after the CMP, performing a steam anneal to the dielectric material.

摘要翻译： 形成浅沟槽隔离区域的方法包括提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 使用旋转将前体填充到开口中; 对前体进行蒸汽固化以产生电介质材料; 在蒸汽固化之后，对电介质材料进行化学机械抛光（CMP）; 并且在CMP之后，对电介质材料进行蒸汽退火。

公开(公告)号：US07642166B2

公开(公告)日：2010-01-05

申请号：US12265736

申请日：2008-11-06

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC分类号： H01L213/8234

CPC分类号： H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

摘要： A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.

摘要翻译： 提供一种制造MOS晶体管器件的方法。 首先，准备具有栅极结构的半导体基板。 栅极结构在侧壁上具有两个侧壁和衬垫。 随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构和衬垫。 接下来，执行激活处理。 此外，将应力覆盖层蚀刻成为自对准硅化物块。 之后，进行自对准处理以在未被应力覆盖层覆盖的区域上形成硅化物层。

公开(公告)号：US07544603B2

公开(公告)日：2009-06-09

申请号：US11233831

申请日：2005-09-22

申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

IPC分类号： H01L21/20

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A method of fabricating a silicon nitride layer is described. First, a substrate is provided. Then, a silicon nitride layer is formed on the substrate. The silicon nitride layer is UV-cured in an atmosphere lower than the standard atmospheric pressure. Through the UV curing treatment, the tensile stress of the silicon nitride layer is increased.

摘要翻译： 描述了制造氮化硅层的方法。 首先，提供基板。 然后，在基板上形成氮化硅层。 氮化硅层在低于标准大气压的气氛中UV固化。 通过UV固化处理，氮化硅层的拉伸应力增加。

公开(公告)号：US20090104773A1

公开(公告)日：2009-04-23

申请号：US12345670

申请日：2008-12-30

申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC分类号： H01L21/768

CPC分类号： H01L21/76801 ,  H01L21/76837 ,  H01L29/78

摘要： A substrate having at least two metal oxide semiconductor devices of a same conductive type and a gap formed between the two devices is provided. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate, filling the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. The first stress layer and the second stress layer provide a same type of stress. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.

摘要翻译： 提供了具有至少两个相同导电类型的金属氧化物半导体器件和在两个器件之间形成的间隙的衬底。 第一应力层形成在衬底上以覆盖金属氧化物半导体器件和衬底，填补间隙。 然后执行回蚀处理以去除间隙内部的应力材料层的一部分。 第一应力层和电介质层依次形成在第一应力层上。 第一应力层和第二应力层提供相同类型的应力。 去除第二应力层的一部分以形成接触开口。 将第二导电层填充到接触开口中以形成接触。

公开(公告)号：US20090068805A1

公开(公告)日：2009-03-12

申请号：US12265736

申请日：2008-11-06

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

摘要： A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.

摘要翻译： 提供一种制造MOS晶体管器件的方法。 首先，准备具有栅极结构的半导体基板。 栅极结构在侧壁上具有两个侧壁和衬垫。 随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构和衬垫。 接下来，执行激活处理。 此外，将应力覆盖层蚀刻成为自对准硅化物块。 之后，进行自对准处理以在未被应力覆盖层覆盖的区域上形成硅化物层。

公开(公告)号：US20080305600A1

公开(公告)日：2008-12-11

申请号：US11758623

申请日：2007-06-05

申请人： Hsiu-Lien Liao ,  Neng-Kuo Chen ,  Teng-Chun Tsai ,  Yi-Wei Chen

发明人： Hsiu-Lien Liao ,  Neng-Kuo Chen ,  Teng-Chun Tsai ,  Yi-Wei Chen

IPC分类号： H01L21/336 ,  H01J37/08

CPC分类号： H01L21/324 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7843

摘要： A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature.

摘要翻译： 用于制造高拉伸应力膜的方法和设备包括提供基板，在基板上形成多应力器，并且执行紫外线快速热处理（UVRTP），用于固化聚应力器并调整其拉伸应力状态，因此 多应力器作为高拉伸应力膜。 由于来自光子和热的能量的组合，高拉伸应力膜的拉伸应力状态在相对较短的工艺周期或相对较低的温度下调节。

公开(公告)号：US20080242020A1

公开(公告)日：2008-10-02

申请号：US11692912

申请日：2007-03-28

申请人： Jei-Ming Chen ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Shih-Wei Sun

发明人： Jei-Ming Chen ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Shih-Wei Sun

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate and a gate structure positioned on the semiconductor substrate are prepared first. A source region and a drain region are included in the semiconductor substrate on two opposite sides of the gate structure. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Next, an inert gas treatment is performed to change a stress value of the stressed cap layer. Because the stress value of the stressed cap layer can be adjusted easily by means of the present invention, one stressed cap layer can be applied to both the N-type MOS transistor and the P-type MOS transistor.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 首先制备位于半导体衬底上的半导体衬底和栅极结构。 源极区域和漏极区域包括在栅极结构的两个相对侧上的半导体衬底中。 随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构，源极区和漏极区。 接下来，进行惰性气体处理以改变应力帽层的应力值。 由于通过本发明可以容易地调整应力覆盖层的应力值，因此可以将一个应力覆盖层施加到N型MOS晶体管和P型MOS晶体管两者。

公开(公告)号：US20080237658A1

公开(公告)日：2008-10-02

申请号：US11691213

申请日：2007-03-26

申请人： Hsiu-Lien Liao ,  Neng-Kuo Chen ,  Jei-Ming Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

发明人： Hsiu-Lien Liao ,  Neng-Kuo Chen ,  Jei-Ming Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC分类号： H01L29/78

CPC分类号： H01L21/76834 ,  H01L21/76825 ,  H01L21/76832 ,  H01L29/7843

摘要： A method of fabricating a semiconductor device is provided. A MOS transistor is formed on a substrate, and then a contact etching stop layer (CESL) is formed over the substrate. A first UV-curing process is performed to increase the stress of the CESL. A dielectric layer is formed on the CESL, and then a second UV-curing process is performed to increase the stress of the dielectric layer. A CMP process is conducted, and then a cap layer is formed on the dielectric layer.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成MOS晶体管，然后在衬底上形成接触蚀刻停止层（CESL）。 执行第一次UV固化过程以增加CESL的应力。 在CESL上形成介电层，然后进行第二次紫外线固化处理以增加介电层的应力。 进行CMP工艺，然后在电介质层上形成覆盖层。

公开(公告)号：US20080153290A1

公开(公告)日：2008-06-26

申请号：US11963999

申请日：2007-12-24

申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC分类号： H01L21/768

CPC分类号： H01L21/76837 ,  H01L21/76801

摘要： A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate. The first stress layer is formed by first forming a first stress material layer over the substrate to cover the metal-oxide semiconductor devices and to fill the gap, the stress material inside the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.

摘要翻译： 提供了形成接触的方法。 提供具有至少两个金属氧化物半导体器件的衬底，并且在两个器件之间形成间隙。 在衬底上形成第一应力层以覆盖金属氧化物半导体器件和衬底。 第一应力层通过首先在衬底上形成第一应力材料层以覆盖金属氧化物半导体器件并填充间隙中的应力材料形成。 然后执行回蚀处理以去除间隙内部的应力材料层的一部分。 第一应力层和电介质层依次形成在第一应力层上。 去除第二应力层的一部分以形成接触开口。 将第二导电层填充到接触开口中以形成接触。

公开(公告)号：US20080023842A1

公开(公告)日：2008-01-31

申请号：US11838892

申请日：2007-08-15

申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC分类号： H01L23/48

CPC分类号： H01L21/76837 ,  H01L21/76801

摘要： A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate. The first stress layer is formed by first forming a first stress material layer over the substrate to cover the metal-oxide semiconductor devices and to fill the gap, wherein the stress material inside the gap has a seam. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.

摘要翻译： 提供了形成接触的方法。 提供具有至少两个金属氧化物半导体器件的衬底，并且在两个器件之间形成间隙。 在衬底上形成第一应力层以覆盖金属氧化物半导体器件和衬底。 第一应力层通过首先在衬底上形成覆盖金属氧化物半导体器件并填充间隙的第一应力材料层形成，其中间隙内的应力材料具有接缝。 然后执行回蚀处理以去除间隙内部的应力材料层的一部分。 第一应力层和电介质层依次形成在第一应力层上。 去除第二应力层的一部分以形成接触开口。 将第二导电层填充到接触开口中以形成接触。