Method for forming interconnect structures
    1.
    发明授权
    Method for forming interconnect structures 有权
    形成互连结构的方法

    公开(公告)号:US09245792B2

    公开(公告)日:2016-01-26

    申请号:US12179991

    申请日:2008-07-25

    摘要: Methods of fabricating interconnect structures in a semiconductor integrated circuit (IC) are presented. A preferred embodiment comprises forming interconnect lines and vias through a dual-damascenes process. It includes forming a via dielectric layer, an etch stop layer directly over the via dielectric layer, and a trench dielectric layer over the etch stop layer. The etch stop layer is patterned through a first photolithography and etch process to form openings in the etch stop layer, prior to the formation of the trench dielectric layer. A second photolithography and etch process is performed after formation of the trench dielectric layer to create trench openings in the trench dielectric layer and via openings in the via dielectric layer, where the patterned etch stop layer acts as a hard-mask in forming vias in the via dielectric layer.

    摘要翻译: 提出了在半导体集成电路(IC)中制造互连结构的方法。 优选实施例包括通过双重镶嵌工艺形成互连线和通孔。 它包括形成通孔电介质层,直接在通孔电介质层上的蚀刻停止层,以及在蚀刻停止层上的沟槽电介质层。 在形成沟槽电介质层之前,蚀刻停止层通过第一光刻和蚀刻工艺图案化以在蚀刻停止层中形成开口。 在形成沟槽电介质层之后进行第二光刻和蚀刻工艺,以在通孔电介质层中的沟槽电介质层和通孔中形成沟槽开口,其中图案化的蚀刻停止层在形成通孔的过程中用作硬掩模 通过电介质层。

    Hybrid STI gap-filling approach
    2.
    发明授权
    Hybrid STI gap-filling approach 有权
    混合STI间隙填充方法

    公开(公告)号:US08319311B2

    公开(公告)日:2012-11-27

    申请号:US12688939

    申请日:2010-01-18

    IPC分类号: H01L29/78

    摘要: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming an opening extending from the top surface into the semiconductor substrate; and performing a first deposition step to fill a first dielectric material into the opening. The first dielectric material is then recessed. A second deposition step is performed to fill a remaining portion of the opening with a second dielectric material. The second dielectric material is denser than the first dielectric material. The second dielectric material is recessed until a top surface of the second dielectric material is lower than the top surface of the semiconductor substrate.

    摘要翻译: 形成集成电路结构的方法包括提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 以及执行第一沉积步骤以将第一介电材料填充到所述开口中。 然后第一介电材料凹入。 执行第二沉积步骤以用第二电介质材料填充开口的剩余部分。 第二电介质材料比第一电介质材料更致密。 第二电介质材料凹入直到第二电介质材料的顶表面低于半导体衬底的顶表面。

    METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE
    3.
    发明申请
    METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE 有权
    形成浅层隔离结构的方法

    公开(公告)号:US20110195559A1

    公开(公告)日:2011-08-11

    申请号:US12703979

    申请日:2010-02-11

    IPC分类号: H01L21/762

    CPC分类号: H01L21/76224

    摘要: An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed extending from the top surface into the substrate. The trench has sidewalls and a bottom surface. A liner oxide layer is formed on the sidewalls and the bottom surface. The liner oxide layer is treated in a plasma environment comprises at least one of NF3, F2, and BF2. The trench is filled with a dielectric layer.

    摘要翻译: 本公开的实施例包括形成浅沟槽隔离结构的方法。 提供基板。 衬底包括顶表面。 从顶表面延伸到衬底中形成沟槽。 沟槽具有侧壁和底面。 衬里氧化物层形成在侧壁和底表面上。 在等离子体环境中处理衬里氧化物层包括NF3,F2和BF2中的至少一种。 沟槽填充有介电层。

    Selective Etch-Back Process for Semiconductor Devices
    4.
    发明申请
    Selective Etch-Back Process for Semiconductor Devices 有权
    半导体器件的选择性蚀刻过程

    公开(公告)号:US20100190345A1

    公开(公告)日:2010-07-29

    申请号:US12617463

    申请日:2009-11-12

    摘要: A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH3 and NF3, an etch process using a polymer-rich gas, or an H2 etch process.

    摘要翻译: 提供了具有散热片和制造方法的半导体器件。 在衬底上形成图案化掩模。 在衬底中形成沟槽,并且沟槽填充有电介质材料。 此后,去除图案化掩模并执行一个或多个蚀刻工艺以使电介质材料凹陷,其中至少一个蚀刻工艺是蚀刻工艺,该蚀刻工艺除去或防止围绕沟槽侧壁形成栅栏。 蚀刻工艺可以是例如使用NH 3和NF 3的等离子体蚀刻工艺,使用富聚合气体的蚀刻工艺或H 2蚀刻工艺。

    STI FILM PROPERTY USING SOD POST-TREATMENT
    5.
    发明申请
    STI FILM PROPERTY USING SOD POST-TREATMENT 有权
    使用SOD后处理的STI膜性质

    公开(公告)号:US20100022068A1

    公开(公告)日:2010-01-28

    申请号:US12179892

    申请日:2008-07-25

    IPC分类号: H01L21/762

    摘要: A method of forming a shallow trench isolation region includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; filling a precursor into the opening using spin-on; performing a steam cure to the precursor to generate a dielectric material; after the steam cure, performing a chemical mechanical polish (CMP) to the dielectric material; and after the CMP, performing a steam anneal to the dielectric material.

    摘要翻译: 形成浅沟槽隔离区域的方法包括提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 使用旋转将前体填充到开口中; 对前体进行蒸汽固化以产生电介质材料; 在蒸汽固化之后,对电介质材料进行化学机械抛光(CMP); 并且在CMP之后,对电介质材料进行蒸汽退火。

    Shallow Trench Isolation Corner Rounding
    6.
    发明申请
    Shallow Trench Isolation Corner Rounding 有权
    浅沟槽隔离角四舍五入

    公开(公告)号:US20100015776A1

    公开(公告)日:2010-01-21

    申请号:US12173263

    申请日:2008-07-15

    IPC分类号: H01L21/762

    CPC分类号: H01L21/76224 H01L21/76232

    摘要: A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration.

    摘要翻译: 提供了一种用于对浅沟槽隔离件的角进行倒角的方法。 优选实施例包括用电介质填充沟槽并使电介质凹陷以暴露邻近衬底表面的沟槽侧壁的一部分。 然后将衬底在氢环境中退火,氢环境通过硅迁移使浅沟槽隔离的角落圆。

    Hybrid gap-fill approach for STI formation
    7.
    发明授权
    Hybrid gap-fill approach for STI formation 有权
    混合间隙填充方法用于STI形成

    公开(公告)号:US08187948B2

    公开(公告)日:2012-05-29

    申请号:US12032962

    申请日:2008-02-18

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76224

    摘要: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.

    摘要翻译: 提供了形成浅沟槽隔离区域的方法。 该方法包括提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 执行保形沉积方法以将电介质材料填充到开口中; 对所述电介质材料进行第一处理,其中所述第一处理提供足够高的能量以破坏所述电介质材料中的键; 并对介电材料进行蒸汽退火。

    Hybrid STI Gap-Filling Approach
    8.
    发明申请
    Hybrid STI Gap-Filling Approach 有权
    混合STI差距填充方法

    公开(公告)号:US20100230757A1

    公开(公告)日:2010-09-16

    申请号:US12688939

    申请日:2010-01-18

    摘要: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming an opening extending from the top surface into the semiconductor substrate; and performing a first deposition step to fill a first dielectric material into the opening. The first dielectric material is then recessed. A second deposition step is performed to fill a remaining portion of the opening with a second dielectric material. The second dielectric material is denser than the first dielectric material. The second dielectric material is recessed until a top surface of the second dielectric material is lower than the top surface of the semiconductor substrate.

    摘要翻译: 形成集成电路结构的方法包括提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 以及执行第一沉积步骤以将第一介电材料填充到所述开口中。 然后第一介电材料凹入。 执行第二沉积步骤以用第二电介质材料填充开口的剩余部分。 第二电介质材料比第一电介质材料更致密。 第二电介质材料凹入直到第二电介质材料的顶表面低于半导体衬底的顶表面。

    Hybrid Gap-fill Approach for STI Formation
    9.
    发明申请
    Hybrid Gap-fill Approach for STI Formation 有权
    用于STI形成的混合间隙填充方法

    公开(公告)号:US20090209083A1

    公开(公告)日:2009-08-20

    申请号:US12032962

    申请日:2008-02-18

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76224

    摘要: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.

    摘要翻译: 提供了形成浅沟槽隔离区域的方法。 该方法包括提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 执行保形沉积方法以将电介质材料填充到开口中; 对所述电介质材料进行第一处理,其中所述第一处理提供足够高的能量以破坏所述电介质材料中的键; 并对介电材料进行蒸汽退火。

    Method of forming shallow trench isolation structure
    10.
    发明授权
    Method of forming shallow trench isolation structure 有权
    形成浅沟槽隔离结构的方法

    公开(公告)号:US08173516B2

    公开(公告)日:2012-05-08

    申请号:US12703979

    申请日:2010-02-11

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76224

    摘要: An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed extending from the top surface into the substrate. The trench has sidewalls and a bottom surface. A liner oxide layer is formed on the sidewalls and the bottom surface. The liner oxide layer is treated in a plasma environment comprises at least one of NF3, F2, and BF2. The trench is filled with a dielectric layer.

    摘要翻译: 本公开的实施例包括形成浅沟槽隔离结构的方法。 提供基板。 衬底包括顶表面。 从顶表面延伸到衬底中形成沟槽。 沟槽具有侧壁和底面。 衬里氧化物层形成在侧壁和底表面上。 在等离子体环境中处理衬里氧化物层包括NF3,F2和BF2中的至少一种。 沟槽填充有介电层。