公开(公告)号：US07061792B1

公开(公告)日：2006-06-13

申请号：US10215678

申请日：2002-08-10

申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang Lin ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang Lin ,  Andrew J. Franklin

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/412 ,  G11C7/18 ,  G11C2207/002

摘要： In a SRAM structure, power consumption is reduced by providing a structure which allows specific memory cells to be selected using word lines and column select lines, and reducing the load on the column address lines by dividing the load into sectors. The dividing into sectors is achieved by making use of sector select lines for selecting two or more rows of cells, and logically ANDing the sector select lines with the column select lines.

摘要翻译： 在SRAM结构中，通过提供允许使用字线和列选择线选择特定存储器单元的结构来降低功耗，并且通过将负载分成扇区来减少列地址线的负载。 通过使用用于选择两行或多行单元的扇区选择线以及逻辑地将扇区选择线与列选择线进行逻辑运算来实现划分为扇区。

公开(公告)号：US06711051B1

公开(公告)日：2004-03-23

申请号：US10235530

申请日：2002-09-05

申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Weipeng Zhang ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Weipeng Zhang ,  Andrew J. Franklin

IPC分类号： G11C1100

CPC分类号： G11C11/419

摘要： A SRAM system which provides for reduced power consumption. The SRAM system utilizes an array of bit cells. Columns of bit cells in the array are partitioned into sections. Each section of bit cells shares a local bit line. A sector select circuit provides for precharging the local bit lines. The sector select circuit also includes a mux for connecting a local bit line to a global bit line. The sector select circuit includes a device for detecting when a sector select signal and a column select signal are present. When both of these signals are present the sector select circuit couples the local bit line with the global bit line, and disengages the precharging of the local bit line.

摘要翻译： 一种提供降低功耗的SRAM系统。 SRAM系统利用位单元阵列。 阵列中位单元格的列被分割成几个部分。 每个位单元共享一个本地位线。 扇区选择电路用于对本地位线进行预充电。 扇区选择电路还包括用于将局部位线连接到全局位线的多路复用器。 扇区选择电路包括用于检测何时存在扇区选择信号和列选择信号的装置。 当这两个信号都存在时，扇区选择电路将局部位线与全局位线耦合，并且使本地位线的预充电脱离。

公开(公告)号：US06621736B1

公开(公告)日：2003-09-16

申请号：US10091927

申请日：2002-03-05

申请人： Yuri Mirgorodski ,  Pavel Poplevine ,  Mark W. Poulter

发明人： Yuri Mirgorodski ,  Pavel Poplevine ,  Mark W. Poulter

IPC分类号： G11C1604

CPC分类号： G11C16/0425 ,  G11C16/12

摘要： A split-gate flash memory array is programmed, in part, by applying a programming voltage to the row of cells that include the to-be-programmed cells, and an inhibiting voltage to the row of cells that share the same source line as the row that includes the to-be-programmed cells. The inhibiting voltage is greater than zero and less than the programming voltage.

摘要翻译： 分割栅极闪存阵列部分地通过将编程电压施加到包括待编程单元的单元行，以及与该单元阵列共享相同源极线的抑制电压来编程 包括要编程的单元格的行。 抑制电压大于零，小于编程电压。

公开(公告)号：US06384398B1

公开(公告)日：2002-05-07

申请号：US09851203

申请日：2001-05-08

申请人： Alexander Kalnitsky ,  Albert Bergemont ,  Pavel Poplevine

发明人： Alexander Kalnitsky ,  Albert Bergemont ,  Pavel Poplevine

IPC分类号： H01L2700

CPC分类号： H01L27/14654 ,  H01L27/14609 ,  H01L27/1463

摘要： The potential on a pixel cell having a gated diode and a read out transistor is set to an initial level prior to an image integration period. During the image integration period, absorbed photons cause the potential on the pixel cell to change. After the image integration period, the pixel cell is then reset and read out by applying a number of pulses to the gated diode. Each of the pulses causes a fixed amount of charge to be injected into the cell. When the potential on the cell has again returned to the initial level, the number of absorbed photons is determined by counting the number of pulses that were required to return the potential to the initial level. The read out transistor is used to determine when the potential is at the initial level by biasing the transistor to output a current that corresponds to the potential on the pixel cell.

公开(公告)号：US06229739B1

公开(公告)日：2001-05-08

申请号：US09662504

申请日：2000-09-14

申请人： Pavel Poplevine ,  Alexander Kalnitsky ,  Albert Bergemont

发明人： Pavel Poplevine ,  Alexander Kalnitsky ,  Albert Bergemont

IPC分类号： G11C700

CPC分类号： G11C7/065

摘要： A sense amplifier places a low positive voltage, such as 0.1 to 0.3 volts, on a bit line instead of ground when a memory cell is read by utilizing a current source circuit to output a reference current that biases a Schottky diode. The current source circuit is implemented with a Schottky diode that utilizes the reverse-biased leakage current of the diode to form the reference current. The current source circuit can also be implemented with a current mirror circuit.

摘要翻译： 当通过利用电流源电路读出存储单元以输出偏置肖特基二极管的参考电流时，读出放大器将位置线上的低正电压（例如0.1至0.3伏特）置于地线上而不是接地。 电流源电路用肖特基二极管实现，其利用二极管的反向偏置漏电流形成参考电流。 电流源电路也可以用电流镜电路来实现。

公开(公告)号：US06169310A

公开(公告)日：2001-01-02

申请号：US09205110

申请日：1998-12-03

申请人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont ,  Hengyang (James) Lin

发明人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont ,  Hengyang (James) Lin

IPC分类号： H01L2362

CPC分类号： H01L27/0288

摘要： An ESD protection device for use with an integrated circuit that provides a low impedance resistive path between IC pads (including Vdd and Vss pads) when power to the IC is off, while assuring adequate isolation between the IC pads when the power is on. The device includes a semiconductor substrate (typically a p-type Si substrate) and at least two vertically integrated pinch resistors formed in the semiconductor substrate. Each of the vertically integrated pinch resistors is connected to a common electrical discharge line and to a pad. Each of the vertically integrated pinch resistors includes a deep well region and a first surface well region, both of the second conductivity type (typically n-type). The first surface well region circumscribes the deep well region, thereby forming a narrow channel region of the first conductivity type (e.g. p-type) therebetween. When no potential is applied to the first surface well regions (i.e. power is off), the two vertically integrated pinch resistors connected by the common electrical discharge line provide a low impedance resistive path between the pads for shunting ESD current. When a potential is applied to the first surface well region by the IC power supply (i.e. power is on), however, the width of the narrow channel region is pinched-off due to a potential-produced depletion region in the narrow channel region, thereby isolating the pads from each other. A process for the formation of the ESD protection device involves sequential formation of each of the device regions in a semiconductor substrate.

摘要翻译： 一种与集成电路一起使用的ESD保护装置，当IC通电时，在IC焊盘（包括Vdd和Vss焊盘）之间提供低阻抗阻抗路径，同时在电源打开时确保IC焊盘之间的充分隔离。 该器件包括形成在半导体衬底中的半导体衬底（通常为p型Si衬底）和至少两个垂直集成的夹持电阻器。 每个垂直集成的夹持电阻器连接到公共放电线和焊盘。 每个垂直集成的夹持电阻器包括深阱区域和第二表面阱区域，第二导电类型（通常为n型）。 第一表面阱区域围绕深阱区域，从而在其间形成第一导电类型（例如p型）的窄通道区域。 当没有电位施加到第一表面阱区域（即电源关闭）时，通过公共放电线连接的两个垂直集成的夹持电阻器在焊盘之间提供了阻抗ESD阻抗的低阻抗路径，用于分流ESD电流。 然而，当通过IC电源将电势施加到第一表面阱区域（即，电源接通）时，窄通道区域的宽度由于窄沟道区域中的潜在产生的耗尽区而被截断， 从而将焊盘彼此隔离。 用于形成ESD保护装置的方法包括在半导体衬底中顺序地形成每个器件区域。

公开(公告)号：US6078094A

公开(公告)日：2000-06-20

申请号：US196458

申请日：1998-11-19

申请人： Pavel Poplevine ,  Alexander Kalnitsky ,  Albert Bergemont

发明人： Pavel Poplevine ,  Alexander Kalnitsky ,  Albert Bergemont

IPC分类号： H01L27/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/80 ,  H01L29/00

CPC分类号： H01L21/823892 ,  H01L27/092

摘要： An analog circuit starter current source device with automatic shut-down capability. The device includes a semiconductor substrate (typically p-type) with a deep well region (typically n-type) below its surface, a first surface well region (typically n-type) on the surface of the substrate that circumscribes the deep well region, and a narrow channel region (typically p-type) separating the deep well region from the first surface well region. The device also includes a first contact region for connecting the first surface well region to the analog circuit, and a second contact region for connecting a substrate region above the deep well to the analog circuit. The configuration provides a variable-width vertical resistor current path capable of starting an analog circuit and then being automatically shut-down by application of a potential to the first contact region sufficient to produce a depletion region that pinches-off the narrow channel region. A process for forming the starter current source device is also provided. The process includes first providing a semiconductor substrate (e.g. p-type), then forming a deep well region (e.g. n-type) below its surface. This is followed by the formation of a first surface well region (e.g. n-type) on the surface of the substrate such that the first surface well region circumscribes the deep well region, thereby producing a narrow channel (e.g. p-type) therebetween. Finally, a first contact region is formed on the surface of the first surface well region, while a second contact region is formed on the surface of semiconductor substrate above the deep well region.

摘要翻译： 具有自动关机功能的模拟电路起动器电流源装置。 该器件包括在其表面下方具有深阱区（通常为n型）的半导体衬底（通常为p型），在衬底的表面上限定深阱区的第一表面阱区（通常为n型） 以及将深阱区域与第一表面阱区域分离的窄通道区域（通常为p型）。 该装置还包括用于将第一表面阱区域连接到模拟电路的第一接触区域和用于将深井上方的衬底区域连接到模拟电路的第二接触区域。 该配置提供了可变宽度的垂直电阻器电流路径，其能够启动模拟电路，然后通过向第一接触区域施加足以产生夹紧窄沟道区域的耗尽区域的电势自动关闭。 还提供了一种用于形成起动器电流源装置的工艺。 该方法包括首先提供半导体衬底（例如p型），然后在其表面下方形成深阱区域（例如n型）。 接着在衬底的表面上形成第一表面阱区域（例如n型），使得第一表面阱区域围绕深阱区域，从而在其间产生窄通道（例如p型）。 最后，在第一表面阱区域的表面上形成第一接触区域，而在深阱区域上方的半导体衬底的表面上形成第二接触区域。

公开(公告)号：US08213227B2

公开(公告)日：2012-07-03

申请号：US12751012

申请日：2010-03-31

申请人： Pavel Poplevine ,  Ernes Ho ,  Hengyang (James) Lin ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Ernes Ho ,  Hengyang (James) Lin ,  Andrew J. Franklin

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0441 ,  G11C16/10

摘要： A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.

摘要翻译： 非易失性存储器（NVM）单元结构包括具有源极，漏极和体区电极的PMOS程序晶体管和连接到数据存储节点的栅电极; NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅电极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS读取晶体管和连接到数据存储节点的栅电极。

公开(公告)号：US20120014183A1

公开(公告)日：2012-01-19

申请号：US12837835

申请日：2010-07-16

申请人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Andrew J. Franklin

IPC分类号： G11C16/04

CPC分类号： G11C16/0466

摘要： A non-volatile memory (NVM) cell structure comprises an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.

摘要翻译： 非易失性存储器（NVM）单元结构包括NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS数据晶体管和连接到数据存储节点的栅电极。

公开(公告)号：US07656698B1

公开(公告)日：2010-02-02

申请号：US11656650

申请日：2007-01-23

申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang (James) Lin ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang (James) Lin ,  Andrew J. Franklin

IPC分类号： G11C11/00

CPC分类号： G11C14/0063 ,  G11C16/0441

摘要： A 4-transistor non-volatile memory (NVM) cell includes a static random access memory (SRAM) cell structure. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the SRAM cell structure, allows an entire array to be programmed at one cycle. Equalize transistors are utilized to obtain more uniform voltage on the floating gates after an erase operation. Utilization of decoupling pas gates during a read operation results in more charge difference on floating gates of programmed and erased cells.

摘要翻译： 4晶体管非易失性存储器（NVM）单元包括静态随机存取存储器（SRAM）单元结构。 NVM单元采用反向Fowler-Nordheim隧道编程技术，其结合SRAM单元结构允许在一个周期对整个阵列进行编程。 利用均衡晶体管在擦除操作之后在浮动栅极上获得更均匀的电压。 在读取操作期间使用去耦pas门导致编程和擦除单元的浮动栅极上的更多的电荷差异。