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    Active pixel sensor cell with integrating varactor and method for using such cell
    4.
    发明授权
    Active pixel sensor cell with integrating varactor and method for using such cell 有权
    具有积分变容二极管的有源像素传感器单元和使用这种单元的方法

    公开(公告)号：US07262401B2

    公开(公告)日：2007-08-28

    申请号：US11496951

    申请日：2006-08-01

    申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Mark W. Poulter ,  Yuri Mirgorodski

    发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Mark W. Poulter ,  Yuri Mirgorodski

    IPC分类号： H01L27/00 ,  H04N3/14

    CPC分类号： H01L27/14609 ,  H04N5/35572 ,  H04N5/361 ,  H04N5/37452

    摘要： An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.

    摘要翻译： 包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管，用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。 在曝光间隔期间，可以将光电二极管暴露于​​光子，以在光电二极管的第一节点处累积次曝光电荷序列。 在曝光间隔的不同子曝光间隔期间，每个次曝光电荷在第一节点处累积。 在每个复位间隔的每一个期间复位光电二极管，每个复位间隔发生在不同的次曝光间隔之前。 指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言，其中曝光电荷指示所有次曝光电荷的总和。

    Active pixel sensor cell with integrating varactor and method for using such cell
    5.
    发明授权
    Active pixel sensor cell with integrating varactor and method for using such cell 有权
    具有积分变容二极管的有源像素传感器单元和使用这种单元的方法

    公开(公告)号：US07102117B2

    公开(公告)日：2006-09-05

    申请号：US10863058

    申请日：2004-06-08

    申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Mark W. Poulter ,  Yuri Mirgorodski

    发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Mark W. Poulter ,  Yuri Mirgorodski

    IPC分类号： H01L27/00

    CPC分类号： H01L27/14609 ,  H04N5/35572 ,  H04N5/361 ,  H04N5/37452

    摘要： An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.

    摘要翻译： 包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管，用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。 在曝光间隔期间，可以将光电二极管暴露于​​光子，以在光电二极管的第一节点处累积次曝光电荷序列。 在曝光间隔的不同子曝光间隔期间，每个次曝光电荷在第一节点处累积。 在每个复位间隔的每一个期间复位光电二极管，每个复位间隔发生在不同的次曝光间隔之前。 指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言，其中曝光电荷指示所有次曝光电荷的总和。

    Method of erasing an NVM cell that utilizes a gated diode
    9.
    发明授权
    Method of erasing an NVM cell that utilizes a gated diode 有权
    擦除使用门控二极管的NVM单元的方法

    公开(公告)号：US07969790B2

    公开(公告)日：2011-06-28

    申请号：US12884519

    申请日：2010-09-17

    申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  Roozbeh Parsa

    发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  Roozbeh Parsa

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/10 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time.

    摘要翻译： 一种擦除形成在N型半导体材料的深阱中的NVM单元结构的方法，其中NVM单元结构包括形成在N型阱中的PMOS晶体管，PMOS晶体管包括间隔开的p型源极和漏极 在它们之间限定n型沟道区的区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，NMOS晶体管包括间隔开的n型源和限定p型沟道的雨区 导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分 通过插入介电材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其隔开， 包括：在所选择的擦除电压下偏置所述深N型阱; 将PMOS晶体管的源极和漏极区域保持在擦除电压或浮置; 并将控制门保持在地面以进行预先选择的擦除时间。

    Method of forming a region of graded doping concentration in a semiconductor device and related apparatus
    10.
    发明授权
    Method of forming a region of graded doping concentration in a semiconductor device and related apparatus 有权
    在半导体器件和相关装置中形成渐变掺杂浓度区域的方法

    公开(公告)号：US07964485B1

    公开(公告)日：2011-06-21

    申请号：US12589417

    申请日：2009-10-23

    申请人： William French ,  Erika Mazotti ,  Yuri Mirgorodski

    发明人： William French ,  Erika Mazotti ,  Yuri Mirgorodski

    IPC分类号： H01L21/22

    CPC分类号： H01L29/0847 ,  H01L21/2253 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

    摘要： A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.

    摘要翻译： 用于形成半导体器件的掺杂区域的方法包括用掩模掩蔽衬底的一部分。 掩模被配置为在掺杂区域内产生渐变掺杂分布。 该方法还包括使用掩模执行植入物以在衬底中产生掺杂区域和未掺杂区域。 该方法还包括扩散掺杂区域以在掺杂区域中产生渐变掺杂分布。 掩模可以包括具有分布在整个光致抗蚀剂材料中的开口的第一区域，其中开口的尺寸和间隔变化。 掩模还可以包括具有分布在整个开放区域中的光致抗蚀剂材料块的第二区域，其中光刻胶块的尺寸和间距变化。 扩散掺杂区域可以包括施加高温退火以使掺杂和未掺杂区域平滑以产生线性渐变的掺杂分布。