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公开(公告)号：US06320795B1
公开(公告)日：2001-11-20
申请号：US09733225
申请日：2000-12-08
IPC分类号： G11C700
CPC分类号： G11C7/106 , G11C7/1051
摘要： A register file for use within, for example, a microprocessor or other digital processing device includes a register file cell having a pull down transistor that is driven by a static logic circuit (e.g., a NOR gate). During a read operation, the static logic circuit causes the pull down transistor to discharge a dynamic bit line node when a predetermined data value is stored within a data storage area of the register file cell. The logic circuit serves to isolate the input terminal of the pull down transistor from a potentially noisy read signal received by the register file cell, thus preventing noise induced leakage currents from being created. In one embodiment, a bias circuit is provided that applies a bias signal to the pull down transistor during non-read intervals to significantly reduce leakage currents flowing through the pull down transistor at these times.
摘要翻译： 在例如微处理器或其它数字处理装置中使用的寄存器文件包括具有由静态逻辑电路（例如，或非门）驱动的下拉晶体管的寄存器文件单元。 在读取操作期间，当预定数据值存储在寄存器文件单元的数据存储区域内时，静态逻辑电路使下拉晶体管放电动态位线节点。 逻辑电路用于将下拉晶体管的输入端与由寄存器堆单元接收的潜在噪声读信号隔离，从而防止产生噪声感应的漏电流。 在一个实施例中，提供偏置电路，其在非读取间隔期间向下拉晶体管施加偏置信号，以显着减少在这些时间流过下拉晶体管的漏电流。
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公开(公告)号：US06271713B1
公开(公告)日：2001-08-07
申请号：US09311917
申请日：1999-05-14
申请人： Ram K. Krishnamurthy
发明人： Ram K. Krishnamurthy
IPC分类号： H03K301
CPC分类号： H03K19/01721
摘要： In some embodiments, the invention includes a die having a driver circuit. The driver circuit includes a driver input node and a driver output node. An nFET pull-up transistor is connected to the driver output node, and wherein the nFET pull-up transistor is at times forward body biased and the forward body bias is substantially greatest when a signal at the driver input node begins to switch high and substantially least when the switching has already essentially occurred. In some embodiments, the driver includes a first inverter to receive an input signal from the driver input node and provide an inverted input signal at a first inverter output node. The driver includes second inverter to receive the inverted input signal from the first inverter output node and provide a driver output signal at the driver output node. The driver includes an nFET pull-up transistor connected between the driver output node and a power supply node, the nFET pull-up transistor having a gate tied to the driver input node. In some embodiments, the nFET pull-up transistor is at times forward body biased. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，本发明包括具有驱动器电路的管芯。 驱动器电路包括驱动器输入节点和驱动器输出节点。 nFET上拉晶体管连接到驱动器输出节点，并且其中nFET上拉晶体管有时向前偏置，并且当驱动器输入节点处的信号开始高且基本上切换时，正向偏置基本上最大 至少当切换已基本发生时。 在一些实施例中，驱动器包括第一反相器，用于从驱动器输入节点接收输入信号，并在第一反相器输出节点处提供反相输入信号。 驱动器包括第二反相器，用于接收来自第一反相器输出节点的反相输入信号，并在驱动器输出节点处提供驱动器输出信号。 驱动器包括连接在驱动器输出节点和电源节点之间的nFET上拉晶体管，该nFET上拉晶体管具有连接到驱动器输入节点的栅极。 在一些实施例中，nFET上拉晶体管有时是正向偏置的。 描述和要求保护其他实施例。
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公开(公告)号：US6137319A
公开(公告)日：2000-10-24
申请号：US302677
申请日：1999-04-30
CPC分类号： G11C7/067 , H03F3/45188 , H03K5/2481 , H03K5/249
摘要： In some embodiments, the invention includes a reference-free single ended sense amplifier. The sense amplifier includes first and second transistors in a differential pair, the first transistor having a control terminal connected to an input conductor to receive an intermediate signal, the first transistor having a data terminal connected to a node, and the second transistor having a control terminal coupled to the node. The sense amplifier further includes a cross-coupled inverter latch having a first inverter coupled to the first transistor through the node and a second inverter coupled to the second transistor. In some embodiments, the control terminal of the second transistor is tied to the node. The first and second transistors of the differential pair may be pFET transistors or nFET transistors or a combination of them. In some embodiments, the sense amplifier is includes as a part of a domino logic gate. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，本发明包括一个无参考的单端读出放大器。 感测放大器包括差分对中的第一和第二晶体管，第一晶体管具有连接到输入导体的控制端以接收中间信号，第一晶体管具有连接到节点的数据端，并且第二晶体管具有控制 终端耦合到节点。 读出放大器还包括交叉耦合的反相器锁存器，其具有通过节点耦合到第一晶体管的第一反相器和耦合到第二晶体管的第二反相器。 在一些实施例中，第二晶体管的控制端被连接到节点。 差分对的第一和第二晶体管可以是pFET晶体管或nFET晶体管或它们的组合。 在一些实施例中，读出放大器包括作为多米诺逻辑门的一部分。 描述和要求保护其他实施例。
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公开(公告)号：US09634866B2
公开(公告)日：2017-04-25
申请号：US14129544
申请日：2013-09-06
IPC分类号： H04L12/64 , H04L12/933
CPC分类号： H04L12/6418 , G06F15/7825 , H04L49/109 , H04L49/251 , H04L49/252 , H04L49/9042
摘要： Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network.
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35.发明申请公开(公告)号：US20150116019A1
公开(公告)日：2015-04-30
申请号：US14069198
申请日：2013-10-31
IPC分类号： H03K3/037
CPC分类号： H03K3/35625 , H03K3/356104
摘要： Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.
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36.发明申请HARDWARE-EMBEDDED KEY BASED ON RANDOM VARIATIONS OF A STRESS-HARDENED INEGRATED CIRCUIT 有权基于应力硬化电路的随机变化的硬件嵌入式键公开(公告)号：US20140266297A1
公开(公告)日：2014-09-18
申请号：US13889849
申请日：2013-05-08
IPC分类号： H03K19/003
CPC分类号： H03K19/00369 , H03K19/00315
摘要： An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell.
摘要翻译： 被设计成用于断言多个可能的输出状态之一（每个具有相等的概率）的IC单元被实现为基于IC单元内的随机变化来断言多个输出状态中的预定的一个，例如随机过程变化。 IC单元阵列可配置为在上电时提供硬件嵌入式密钥，该特征是选择的IC单元的随机变化的组合，在制造之前和之后都能够防止篡改，并且能够耐老化，瞬时热噪声， 和环境变化，如电压和温度波动。 该密钥可以用作但不限于平台根密钥，高带宽数字内容保护（HDCP）密钥，增强型隐私标识（EPID）密钥和/或高级访问内容系统（AACS）密钥）。 还公开了基于IC电池的输出状态来测量IC电池的稳定性和应力硬化的技术。
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37.发明申请SINGLE INSTRUCTION MULTIPLE DATA (SIMD) RECONFIGURABLE VECTOR REGISTER FILE AND PERMUTATION UNIT 审中-公开单指令多数据（SIMD）可重新配置的矢量寄存器文件和传输单元公开(公告)号：US20130339649A1
公开(公告)日：2013-12-19
申请号：US13524454
申请日：2012-06-15
IPC分类号： G06F12/00
CPC分类号： G09G5/393 , G06F3/14 , G06F9/30032 , G06F9/30036 , G06F9/3012 , G06F9/345 , G09G5/363
摘要： An apparatus may comprise a register file and a permutation unit coupled to the register file. The register file may have a plurality of register banks and an input to receive a selection signal. The selection signal may select one or more unit widths of a register bank as a data element boundary for read or write operations.
摘要翻译： 装置可以包括寄存器文件和耦合到寄存器文件的置换单元。 寄存器文件可以具有多个寄存器组和用于接收选择信号的输入。 选择信号可以选择寄存器组的一个或多个单元宽度作为用于读取或写入操作的数据元素边界。
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公开(公告)号：US08214414B2
公开(公告)日：2012-07-03
申请号：US12242727
申请日：2008-09-30
申请人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
发明人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
IPC分类号： G06F15/00
摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).
摘要翻译： 描述了PopCount和BitScan的合并数据路径。 硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。 选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。 如果选择了BitScan操作，则输入字被编码。 压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。 压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。
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公开(公告)号：US07855575B1
公开(公告)日：2010-12-21
申请号：US12566977
申请日：2009-09-25
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613
摘要： Described herein is the method and apparatus for generating symmetrical level shifted signals by a symmetrical level shifter. The symmetrical level shifter comprises an edge detector operable to generate transition edge based pulses from an input signal based on a first power supply level; a voltage level shifter, coupled with the edge detector, operable to convert the transition edge based pulses based on the first power supply level to edge based pulses based on a second power supply level; and a divider circuit, coupled with the voltage level shifter, operable to generate an output signal from the edge based pulses based on the second power supply level.
摘要翻译： 这里描述了通过对称电平移位器产生对称电平移位信号的方法和装置。 对称电平移位器包括边沿检测器，其可操作以基于第一电源电平从输入信号产生基于过渡沿的脉冲; 与边缘检测器耦合的电压电平移位器可操作以基于第二电源电平将基于第一电源电平的基于边沿的脉冲转换为基于边缘的脉冲; 以及与所述电压电平移位器耦合的分频器电路，用于基于所述第二电源电平从所述基于边沿的脉冲产生输出信号。
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公开(公告)号：US20090167351A1
公开(公告)日：2009-07-02
申请号：US11966307
申请日：2007-12-28
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： A co-processor system is provided that includes an array of configurable logic blocks (CLBs). Each CLB including a plurality of look-up tables and a plurality of adders. Each CLB may be dynamically reconfigurable to perform a plurality of logical functions.
摘要翻译： 提供了包括可配置逻辑块（CLB）阵列的协处理器系统。 每个CLB包括多个查找表和多个加法器。 每个CLB可以是动态可重构的以执行多个逻辑功能。
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