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公开(公告)号：US08577948B2
公开(公告)日：2013-11-05
申请号：US12886012
申请日：2010-09-20
申请人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
发明人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
IPC分类号： G06F7/483
CPC分类号： G06F9/3893 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036
摘要： In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，如果第一和第二操作数的至少一部分与第三操作数之间的差小于阈值，则处理器包括具有第一路径以处理指令的执行的乘法累加（MAC）单元，以及 如果差值大于阈值，则处理指令执行的第二路径。 基于该差异，第三操作数的至少一部分将被提供给MAC单元的乘法器或第二路径的压缩器。 描述和要求保护其他实施例。
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公开(公告)号：US07913101B2
公开(公告)日：2011-03-22
申请号：US11824410
申请日：2007-06-29
申请人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
发明人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
IPC分类号： G06F1/12
CPC分类号： H03K5/135 , H03K2005/00058 , H03K2005/00234 , H03K2005/00241
摘要： A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.
摘要翻译： 一种方法包括：当偏移偏离第一方向的值时，延迟至少一个信号的偏移的第一数量的时钟相位; 以及当所述偏移在所述第二方向上偏离所述值时，将所述至少一个信号的偏移延迟到所述第二数量的时钟相位。 时钟相位的第一个数量与第二个时钟相位数不同。 所述至少一个信号与在每个相应时钟周期中具有多个时钟相位的呈现后续时钟周期的时钟信号基本同步地影响多个后续偏移。
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公开(公告)号：US07840885B2
公开(公告)日：2010-11-23
申请号：US11860493
申请日：2007-09-24
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译： 移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。
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4.发明授权公开(公告)号：US07606062B2
公开(公告)日：2009-10-20
申请号：US12006238
申请日：2007-12-31
IPC分类号： G11C11/40
CPC分类号： G11C11/419
摘要： Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.
摘要翻译： 描述了关于超低电压存储器位单元的方法和装置。 在一个实施例中，使用对由互补写入字线控制的数据存储节点的冗余路径提供超低电压存储器件。 还描述了其它实施例。
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公开(公告)号：US20090085637A1
公开(公告)日：2009-04-02
申请号：US11906166
申请日：2007-09-28
IPC分类号： H03L5/00
CPC分类号： H03K19/0175 , H03K3/356139
摘要： An apparatus includes: a signal receiving unit receiving an input signal and presenting a first signal varying within a first signal range; a signal treating unit coupled with the signal receiving unit, receiving the first signal and presenting a second signal varying within a second signal range; and an output unit coupled with the signal treating unit. The signal treating unit and the output unit receive a control signal. The signal treating unit responds to the control signal to provide the second signal to the output unit when the control signal has a first value and to not provide the second signal to the output unit when the control signal has a second value. The output unit permits presentation of an output signal when the control signal has the first value and establishes the output signal at a predetermined value when the control signal has the second value.
摘要翻译： 一种装置包括：信号接收单元，接收输入信号并呈现在第一信号范围内变化的第一信号; 与所述信号接收单元耦合的信号处理单元，接收所述第一信号并呈现在第二信号范围内变化的第二信号; 以及与信号处理单元耦合的输出单元。 信号处理单元和输出单元接收控制信号。 当控制信号具有第一值时，信号处理单元响应控制信号以向输出单元提供第二信号，并且当控制信号具有第二值时，信号处理单元不向输出单元提供第二信号。 当控制信号具有第一值时，输出单元允许呈现输出信号，并且当控制信号具有第二值时，输出单元确定输出信号为预定值。
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公开(公告)号：US07352209B2
公开(公告)日：2008-04-01
申请号：US11411647
申请日：2006-04-26
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012
摘要： A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.
摘要翻译： 电压电平转换器包括静态电压电平转换器和耦合到静态电压电平转换器的分离电平输出电路。 在另一实施例中，电压电平转换器包括静态电压电平转换器，第一晶体管和第二晶体管。 静态电压电平转换器包括输入节点，第一上拉节点，第二上拉节点，逆变器输出节点和输出节点。 第一晶体管耦合到输入节点和第一上拉节点。 第二晶体管耦合到第二上拉节点和逆变器输出节点。
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公开(公告)号：US07272029B2
公开(公告)日：2007-09-18
申请号：US11025778
申请日：2004-12-29
IPC分类号： G11C11/00
摘要： A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.
摘要翻译： 读出放大器转换将输出信号编码到总线上，使得当感测到的位线具有与先前感测的位线的状态不同的状态时，总线信号仅转变。 读出放大器包括当总线信号被断言时改变状态的存储元件。 基于存储元件的状态，读出放大器的输出有条件地反转。
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公开(公告)号：US06762957B2
公开(公告)日：2004-07-13
申请号：US10027795
申请日：2001-12-20
IPC分类号： G11C710
CPC分类号： H03K3/356139 , H03K3/012
摘要： A dual-supply voltage latch includes a data input node to receive an input data, internal nodes to hold the input data, and an output node to output an output data. The latch also includes clock input nodes to receive a clock signal. The data input, internal, and data output nodes are at a higher potential than the clock nodes. Since clock nodes are high activity nodes, less potential on these nodes reduces the energy consumed by the latch. Although the data nodes and clock nodes are at different potentials, the latch has reduced static power dissipation.
摘要翻译： 双电源电压锁存器包括用于接收输入数据的数据输入节点，用于保存输入数据的内部节点以及输出输出数据的输出节点。 锁存器还包括时钟输入节点以接收时钟信号。 数据输入，内部和数据输出节点处于比时钟节点更高的电位。 由于时钟节点是高活动节点，所以这些节点上的较小电位降低了锁存器消耗的能量。 虽然数据节点和时钟节点处于不同的电位，但锁存器降低了静态功耗。
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公开(公告)号：US06751141B1
公开(公告)日：2004-06-15
申请号：US10305703
申请日：2002-11-26
IPC分类号： G11C702
摘要： A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.
摘要翻译： 一种用于读取SRAM中的存储单元的读出放大器，读出放大器包括两个栅极偏置的pMOSFET，每个对应于选定的位线。 两个栅极偏置的pMOSFET的栅极将其栅极偏置到偏置电压，其源极通过列选择晶体管耦合到所选位线，并且其漏极通过传输晶体管耦合到两个交叉耦合的反相器的两个端口， 交叉耦合的逆变器形成锁存器。 在选择的位线对已被预充电并且预充电阶段结束之后，两个栅极偏置的pMOSFET中的一个快速进入其亚阈值区域，其中一个位线通过其相应的存储单元放电，从而切断位线的电容 从感测放大器。 当通过晶体管使能时，两个pMOSFET中的另一个允许显着的位线电荷通过其对应的传输晶体管传输到其相应的端口，而相对较小的电荷被传送到另一个端口。 该电荷转移方案允许在端口处快速产生差分电压，从而以降低的功率消耗提供快速锁存和读取操作。 位线电压摆幅也可以降低以降低功耗。
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公开(公告)号：US06628143B2
公开(公告)日：2003-09-30
申请号：US09965360
申请日：2001-09-26
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.
摘要翻译： 全驱动，源极跟随器泄漏容限动态逻辑门的实施例包括nMOSFET逻辑，用于在评估阶段对节点进行有条件充电，并且在预充电阶段期间将节点充电至相对小的电压，使得nMOSFET 逻辑变为反向偏置。
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