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    Write driver with power optimization and interconnect impedance matching
    31.
    发明授权
    Write driver with power optimization and interconnect impedance matching 有权
    写入驱动器，具有电源优化和互连阻抗匹配

    公开(公告)号：US07375909B2

    公开(公告)日：2008-05-20

    申请号：US10824096

    申请日：2004-04-14

    Applicant: Alessandro Venca ,  Roberto Alini ,  Baris Posat

    Inventor： Alessandro Venca ,  Roberto Alini ,  Baris Posat

    IPC: G11B5/09

    CPC classification number: G11B5/02

    Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

    Abstract translation: 用于通过互连或柔性传输线连接到写入头的写入头来驱动写入电流的写入驱动器。 写驱动器包括将写驱动器的输出阻抗与互连的奇特特性阻抗匹配的电路，并且包括产生到写头的电流输出的电流源。 写入驱动器提供电流放大效应，因为输出电流是通过写入线圈驱动的写入电流的一半。 阻抗匹配电路包括具有等于互连的奇特性阻抗的电阻的输出电阻器。 写入驱动器包括电压源，其操作以在互连的传输延迟的两倍的初始周期期间在输出电阻器上保持零电压降。

    Write driver with improved boosting circuit and interconnect impedance matching
    32.
    发明授权
    Write driver with improved boosting circuit and interconnect impedance matching 有权
    写驱动器具有改进的升压电路和互连阻抗匹配

    公开(公告)号：US07365928B2

    公开(公告)日：2008-04-29

    申请号：US11105174

    申请日：2005-04-13

    Applicant: Alessandro Venca ,  Roberto Alini ,  Baris Posat

    Inventor： Alessandro Venca ,  Roberto Alini ,  Baris Posat

    IPC: G11B5/02

    CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

    Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a pair of current sources, such as MOS transistors, connected to the input node of a single capacitor. During the overshoot duration, the current sources selectively operate at saturation to generate a pulsed current with an amplitude of half the load current. The recharge of the capacitor is done with the load current.

    Abstract translation: 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到单个电容器的输入节点的一对电流源，例如MOS晶体管。 在过冲持续时间期间，电流源选择性地工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电容器的充电由负载电流完成。

    One-time programmable circuit exploiting BJT hFE degradation
    34.
    发明申请
    One-time programmable circuit exploiting BJT hFE degradation 有权
    一次性可编程电路利用BJT hFE降解

    公开(公告)号：US20060262590A1

    公开(公告)日：2006-11-23

    申请号：US11115538

    申请日：2005-04-27

    Applicant: Roberto Alini ,  Sergio Rovati ,  Eric Vandenbossche ,  Christopher Paskins

    Inventor： Roberto Alini ,  Sergio Rovati ,  Eric Vandenbossche ,  Christopher Paskins

    IPC: G11C17/00

    CPC classification number: G11C17/16

    Abstract: A one-time programmable circuit uses forced BJT hFE degradation to permanently store digital information as a logic zero or logic one state. The forced degradation is accomplished by applying a voltage or current to the BJT for a specific time to the reversed biased base-emitter junction, allowing a significant degradation of the junction without destroying it.

    Abstract translation: 一次性可编程电路使用强制BJT低电平劣化将数字信息永久存储为逻辑0或逻辑1状态。 强制退化是通过向BJT施加一个特定时间的电压或电流到反向偏置的基极 - 发射极接点来实现的，从而允许接合处的显着劣化而不破坏它。

    Write head driver circuit and method for writing to a memory disk
    35.
    发明授权
    Write head driver circuit and method for writing to a memory disk 有权
    写头驱动电路和写入存储盘的方法

    公开(公告)号：US06970316B2

    公开(公告)日：2005-11-29

    申请号：US09991557

    申请日：2001-11-09

    Applicant: Alessandro Venca ,  Baris Posat ,  Kemal Ozanoglu ,  Roberto Alini

    Inventor： Alessandro Venca ,  Baris Posat ,  Kemal Ozanoglu ,  Roberto Alini

    IPC: G11B5/09 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02 ,  G11B15/12

    CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013

    Abstract: A circuit and method are disclosed for relatively rapidly causing the current flowing through a write head to transition between steady states without generating an appreciable amount of capacitively-coupled noise. Embodiments of the present invention generally provide drive voltage signals to the write head that have no common mode voltage levels during transitions between steady state current levels in the write head. In other words, the drive voltage signals applied to the write head are substantially entirely differential during write head current transitions. In an exemplary embodiment of the present invention, a driver circuit includes switching circuitry connected between the terminals of the write head and reference voltage supplies, such as positive and negative voltage supplies. The driver circuit further includes timing circuitry that generates control signals for controlling the switching circuitry.

    Abstract translation: 公开了一种电路和方法，用于相对快速地使流过写入头的电流在稳态之间转变而不产生可观量的电容耦合噪声。 本发明的实施例通常向写入头提供在写入头中的稳态电流电平之间的转换期间不具有共模电压电平的驱动电压信号。 换句话说，施加到写入头的驱动电压信号在写入头电流转换期间基本上完全不同。 在本发明的示例性实施例中，驱动器电路包括连接在写入头的端子和参考电压源（例如正和负电压源）之间的开关电路。 驱动器电路还包括产生用于控制开关电路的控制信号的定时电路。

    Voltage regulator operable over a wide range of supply voltage
    36.
    发明授权
    Voltage regulator operable over a wide range of supply voltage 有权
    电压调节器可在宽范围的电源电压下工作

    公开(公告)号：US06963460B2

    公开(公告)日：2005-11-08

    申请号：US10295263

    申请日：2002-11-14

    Applicant: Manish Jain ,  Roberto Alini

    Inventor： Manish Jain ,  Roberto Alini

    IPC: G11B20/10 ,  G05F1/10 ,  G11B5/02 ,  G11B5/09 ,  G11B19/00

    CPC classification number: G11B19/00 ,  G11B19/2063

    Abstract: A voltage regulator includes an output node and first and second regulator circuits. The first regulator circuit generates a first regulated voltage on the output node when a supply voltage equals or exceeds a predetermined threshold, and the second regulator circuit generates a second regulated voltage on the output node when the supply voltage is less than the predetermined threshold.

    Abstract translation: 电压调节器包括输出节点和第一和第二调节器电路。 当电源电压等于或超过预定阈值时，第一调节器电路在输出节点上产生第一调节电压，并且当电源电压小于预定阈值时，第二调节器电路在输出节点上产生第二调节电压。

    Write driver with improved boosting circuit and interconnect impedance matching
    37.
    发明申请
    Write driver with improved boosting circuit and interconnect impedance matching 有权
    写驱动器具有改进的升压电路和互连阻抗匹配

    公开(公告)号：US20050237785A1

    公开(公告)日：2005-10-27

    申请号：US11105174

    申请日：2005-04-13

    Applicant: Alessandro Venca ,  Roberto Alini ,  Baris Posat

    Inventor： Alessandro Venca ,  Roberto Alini ,  Baris Posat

    IPC: G05F3/26 ,  G11B5/00 ,  G11B5/02 ,  G11B5/09 ,  H02M3/07 ,  G11C11/00

    CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

    Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a pair of current sources, such as MOS transistors, connected to the input node of a single capacitor. During the overshoot duration, the current sources selectively operate at saturation to generate a pulsed current with an amplitude of half the load current. The recharge of the capacitor is done with the load current.

    Abstract translation: 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到单个电容器的输入节点的一对电流源，例如MOS晶体管。 在过冲持续时间期间，电流源选择性地工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电容器的充电由负载电流完成。

    Basic cell for programmable analog time-continuous filter
    39.
    发明授权
    Basic cell for programmable analog time-continuous filter 失效
    可编程模拟时间连续滤波器的基本单元

    公开(公告)号：US06359503B1

    公开(公告)日：2002-03-19

    申请号：US08999962

    申请日：1997-08-12

    Applicant: Roberto Alini ,  Francesco Brianti ,  Valerio Pisati ,  Marco Demicheli

    Inventor： Roberto Alini ,  Francesco Brianti ,  Valerio Pisati ,  Marco Demicheli

    IPC: H03K500

    CPC classification number: H03H15/00 ,  H02P6/21 ,  H03H11/0422

    Abstract: An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage provided with a pair of structurally identical transconductance half-cells connected together in a common circuit node. With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines connected through multiplier nodes to a final summation node. “Elementary cell structure for programmable time-continuous analog filters and in particular for read/write operations on magnetic supports and associated analog filter”

    Abstract translation: 用于可编程时间连续模拟滤波器的基本单元结构，特别是用于在磁性支撑上的读取/写入操作中处理模拟信号的基本单元结构包括：放大器级，其设置有一对在公共电路节点中连接在一起的结构相同的跨导半电池 。 这种类型的单元级联提供了一种时间连续的模拟延迟线，其用于横向时间连续的模拟滤波器。 该滤波器包括通过乘法器节点连接到最终求和节点的相同延迟线级联。 “用于可编程时间连续模拟滤波器的基本单元结构，特别是用于磁性支持和相关模拟滤波器的读/写操作”

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