公开(公告)号：US06775752B1

公开(公告)日：2004-08-10

申请号：US09510288

申请日：2000-02-21

Applicant: Rohit Bhatia ,  David P Hannum

Inventor： Rohit Bhatia ,  David P Hannum

IPC: G06F1200

CPC classification number: G06F9/3865 ,  G06F9/383 ,  G06F9/3842

Abstract: The present invention relates to a mechanism for updating a fully associative array which is used to store entries associated with speculated instructions. Preferably, the array includes a plurality of data banks for storing entries, a plurality of ports for writing to the plurality of data banks, pointers associated with the respective banks for identifying table locations suitable for overwriting by upcoming entries, wherein an entry is suitable for overwriting when it is deemed invalid by the inventive system. A preferred embodiment is disclosed involving two ports writing to two banks wherein a plurality of factors is considered in deciding where prospective entries from the two ports will be written in the table. The Factors include, matches between existing and prospective entries, the default designated data bank for a given port, whether two write operations are being attempted simultaneously, and the number of entries already present in each data bank.

Abstract translation: 本发明涉及用于更新完全关联数组的机制，其用于存储与推测指令相关联的条目。 优选地，阵列包括用于存储条目的多个数据库，用于向多个数据库写入的多个端口，与各个存储体相关联的指针，用于识别适合于即将到来的条目覆盖的表位置，其中条目适合于 当本发明系统被认为无效时重写。 公开了一个优选实施例，其涉及写入两个存储体的两个端口，其中考虑多个因素来决定来自两个端口的预期条目将被写入表中。 这些因素包括现有和预期条目之间的匹配，给定端口的默认指定数据库，是否同时尝试两个写入操作以及每个数据库中已存在的条目数。

公开(公告)号：US06636960B1

公开(公告)日：2003-10-21

申请号：US09505093

申请日：2000-02-16

Applicant: James Douglas Gibson ,  Rohit Bhatia

Inventor： James Douglas Gibson ,  Rohit Bhatia

IPC: G06F940

CPC classification number: G06F9/3865 ,  G06F9/30167 ,  G06F9/3842

Abstract: The system is a method and an apparatus for resteering failing speculation check instructions in the pipeline of a processor. A branch offset immediate value and an instruction pointer correspond to each failing instruction. These values are used to determine the correct target recovery address. A relative adder adds the immediate value and the instruction pointer value to arrive at the target recovery address. This is done by flushing the pipeline upon the occurrence of a failing speculation check instruction. The pipeline flush is extended to allow the instruction stream to be resteered. The immediate value and the instruction pointer are then routed through the existing data paths of the pipeline, into the relative adder, which calculates the correct address. A sequencer tracks the progression of these values through the pipeline and causes a branch at the desired time.

Abstract translation: 该系统是用于重新排列处理器流水线中的失败的投机检查指令的方法和装置。 分支偏移立即值和指令指针对应于每个失败的指令。 这些值用于确定正确的目标恢复地址。 相关加法器将立即值和指令指针值相加，以达到目标恢复地址。 这是通过在发生失败的猜测检查指令时冲洗管道来完成的。 扩展管道刷新以允许指令流被重新启动。 然后立即值和指令指针通过流水线的现有数据路径被路由到相对加法器中，该加法器计算正确的地址。 定序器通过管道跟踪这些值的进度，并在所需时间引起分支。

公开(公告)号：US20140075123A1

公开(公告)日：2014-03-13

申请号：US13613777

申请日：2012-09-13

Applicant: Gur HILDESHEIM ,  Chang Kian TAN ,  Robert S. CHAPPELL ,  Rohit BHATIA

Inventor： Gur HILDESHEIM ,  Chang Kian TAN ,  Robert S. CHAPPELL ,  Rohit BHATIA

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/651 ,  G06F2212/655 ,  G06F2212/681 ,  G06F2212/684

Abstract: In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并从寻呼结构获得物理地址的对应部分，与第一步行者同时操作的第二步行者， 逻辑，用于防止第一步行者将所获得的物理地址部分存储在响应于第一线性地址部分匹配第二步行者的并发寻呼结构访问的相应线性地址部分的寻呼高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US08538849B2

公开(公告)日：2013-09-17

申请号：US13190655

申请日：2011-07-26

Applicant: Michael Schmanske ,  Maneesh Deshpande ,  Rohit Bhatia ,  Yidong Ding ,  Pankaj Khandelwal

Inventor： Michael Schmanske ,  Maneesh Deshpande ,  Rohit Bhatia ,  Yidong Ding ,  Pankaj Khandelwal

IPC: G06Q40/00

CPC classification number: G06Q40/04 ,  G06Q40/06

Abstract: An exemplary aspect comprises receiving data related to an underlying asset; calculating values corresponding to near-term implied volatility and realized volatility for the underlying asset; and transmitting data sufficient to describe an index based on a difference between the values corresponding to the near-term implied volatility and the realized volatility for the underlying asset. Another exemplary aspect comprises receiving electronic data related to an underlying asset; calculating data sufficient to describe a plurality of call options and a plurality of put options related to the underlying asset and written on a first settlement date; crediting an account with proceeds from selling the call and put options; and debiting the account to settle one or more of the options that are in-the-money on a second settlement date. Other aspects are apparent from the description and claims.

Abstract translation: 示例性方面包括接收与标的资产相关的数据; 计算相应资产的近期隐含波动率和实现波动率的值; 并且基于与短期隐含波动率相对应的值与标的资产的实现波动率之间的差异来传送足以描述指数的数据。 另一示例性方面包括接收与标的资产相关的电子数据; 计算足以描述多个看涨期权的数据和与相关资产相关并在第一结算日期写入的多个看跌期权; 记入销售电话和放置期权的收益; 并借记帐户以在第二个结算日期结算一个或多个在货币中的期权。 从描述和权利要求中，其它方面是显而易见的。

公开(公告)号：US08219780B2

公开(公告)日：2012-07-10

申请号：US11228058

申请日：2005-09-16

Applicant: James R. Callister ,  Eric R. Delano ,  Rohit Bhatia ,  Shawn Kenneth Walker ,  Mark M. Gibson

Inventor： James R. Callister ,  Eric R. Delano ,  Rohit Bhatia ,  Shawn Kenneth Walker ,  Mark M. Gibson

IPC: G06F12/00

CPC classification number: G06F12/1027 ,  G06F12/0842

Abstract: Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.

Abstract translation: 描述了与减轻上下文切换高速缓存和TLB未命中的影响相关联的系统，方法，媒体和其他实施例。 一个示例性系统实施例包括被配置为运行多处理虚拟存储器操作系统的处理器。 处理器可以可操作地连接到存储器，并且可以包括被配置为存储TLB条目的高速缓存和翻译后备缓冲器（TLB）。 示例性系统可以包括上下文控制逻辑，其被配置为选择性地将数据从TLB复制到数据存储器，用于从处理器交换出的第一进程，并且将数据从数据存储选择性地复制到TLB，以将第二进程交换到 到处理器。

公开(公告)号：US20080243967A1

公开(公告)日：2008-10-02

申请号：US11729441

申请日：2007-03-29

Applicant: Rohit Bhatia ,  Subodh Kumar ,  Nitin Mukhija ,  Abhishek Agarwal

Inventor： Rohit Bhatia ,  Subodh Kumar ,  Nitin Mukhija ,  Abhishek Agarwal

IPC: G06F12/00

CPC classification number: G06F17/30489

Abstract: Duplicate record processing is enabled employing on customizable rules. Detected duplicate records are merged, deleted, deactivated, or moved based on one or more sets of customizable rules. Different rule sets may be used for each record type, or a rule set reused for different records. Hierarchical relationships between master and child records are adjusted upon duplicate processing based on rules and/or record attributes.

Abstract translation: 启用了可定制规则的重复记录处理。 根据一套或多套可自定义规则合并，删除，停用或移动检测到的重复记录。 可以为每个记录类型使用不同的规则集，或者可以为不同的记录重用规则集。 基于规则和/或记录属性的重复处理来调整主记录和子记录之间的分层关系。

公开(公告)号：US07213134B2

公开(公告)日：2007-05-01

申请号：US10092670

申请日：2002-03-06

Applicant: Donald C. Soltis, Jr. ,  Rohit Bhatia

Inventor： Donald C. Soltis, Jr. ,  Rohit Bhatia

IPC: G06F9/48

CPC classification number: G06F9/3851

Abstract: A processing unit of the invention has multiple instruction pipelines for processing multi-threaded instructions. Each thread may have an urgency associated with its program instructions. The processing unit has a thread switch controller to monitor processing of instructions through the various pipelines. The thread controller also controls switch events to move from one thread to another within the pipelines. The controller may modify the urgency of any thread such as by issuing an additional instruction. The thread controller preferably utilizes certain heuristics in making switch event decisions. A time slice expiration unit may also monitor expiration of threads for a given time slice.

Abstract translation: 本发明的处理单元具有用于处理多线程指令的多条指令流水线。 每个线程可能具有与其程序指令相关联的紧急性。 处理单元具有线程开关控制器，用于监视通过各种管线的指令处理。 线程控制器还控制开关事件在管道内从一个线程移动到另一个线程。 控制器可以通过发出附加指令来修改任何线程的紧急性。 螺纹控制器优选地在确定开关事件决定时利用某些启发式。 时间片过期单元还可以监视给定时间片的线程的到期时间。

公开(公告)号：US20070043929A1

公开(公告)日：2007-02-22

申请号：US11205622

申请日：2005-08-17

Applicant: Kevin Safford ,  Rohit Bhatia ,  Karl Brummel

Inventor： Kevin Safford ,  Rohit Bhatia ,  Karl Brummel

IPC: G06F12/00

CPC classification number: G06F12/1063 ,  G06F12/1018

Abstract: The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.

Abstract translation: 本发明涉及一种改进的微处理器，具有具有多个可以操作以提供虚拟存储器的高速缓存的存储器系统。 在微处理器中包括的高速缓冲存储器中的是传统的高速缓冲存储器，其存储由微处理器执行的处理使用的数据和指令，并且通常被布置在高速缓存层级中，以及一个或多个转换后备缓冲器（TLB）高速缓存 它存储有限数量的虚拟页面翻译。 改进的微处理器还具有额外的高速缓存，用于存储当TLB未命中时被访问的虚拟散列页表（VHPT）。 引入这种VHPT高速缓存消除或者至少减少了当TLB未命中时微处理器在高速缓存层级的高速缓存或微处理器外部的其他存储器（例如，主存储器）中查找信息的需要，从而增强了微处理器 速度。

公开(公告)号：US20060031679A1

公开(公告)日：2006-02-09

申请号：US10910652

申请日：2004-08-03

Applicant: Donald Soltis ,  Rohit Bhatia ,  Eric DeLano

Inventor： Donald Soltis ,  Rohit Bhatia ,  Eric DeLano

IPC: H04L9/00

CPC classification number: G06F21/6281 ,  G06F2221/2105

Abstract: In a computer system including a plurality of resources, techniques are disclosed for receiving a request from a software program to access a specified one of the plurality of resources, determining whether the specified one of the plurality of resources is a protected resource, and, if the specified one of the plurality of resources is a protected resource, for denying the request if the computer system is operating in a protected mode of operation, and processing the request based on access rights associated with the software program if the computer system is not operating in the protected mode of operation.

Abstract translation: 在包括多个资源的计算机系统中，公开了用于接收来自软件程序的访问多个资源中的指定的资源的请求的技术，确定所述多个资源中的指定的一个资源是否是受保护的资源，以及如果 所述多个资源中的指定的一个资源是受保护的资源，如果所述计算机系统在受保护的操作模式下操作，则拒绝所述请求，以及如果所述计算机系统未运行，则基于与所述软件程序相关联的访问权限来处理所述请求 在受保护的操作模式下。

公开(公告)号：US06745322B1

公开(公告)日：2004-06-01

申请号：US09507505

申请日：2000-02-18

Applicant: Russell C Brockmann ,  Patrick Knebel ,  Kevin David Safford ,  Rohit Bhatia

Inventor： Russell C Brockmann ,  Patrick Knebel ,  Kevin David Safford ,  Rohit Bhatia

IPC: G06F944

CPC classification number: G06F9/30174 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3861

Abstract: A method and apparatus that utilizes a simple test and flush mechanism to implement branch instructions of one Instruction Set Architecture (ISA) using instructions of another ISA is described. During the decoding and sequencing of microinstructions to implement a branch instruction, a fix-up address, which represents the remedial branch target in the event of a mispredicted target or branch condition, is determined and stored. A test condition is set to determine if the prediction or the branch condition was correct. When the test condition fails, the instruction execution pipeline is immediately flushed to avoid executing any instruction remaining in the pipeline following the branch instructions. The flushing of the pipeline signals the instruction fetch control mechanism to redirect the instruction flow to the instruction corresponding to the fix-up address. A method and apparatus according to the present invention further allows flushing of the pipeline when conditions other than ones involved in branch instructions occurs, e.g., to flush stale instructions.

Abstract translation: 描述了使用简单的测试和刷新机制来使用另一个ISA的指令来实现一个指令集架构（ISA）的分支指令的方法和装置。 在实现分支指令的微指令的解码和排序期间，确定并存储在错误的目标或分支条件的情况下表示补救分支目标的修正地址。 设置测试条件以确定预测或分支条件是否正确。 当测试条件失败时，立即刷新指令执行流水线，以避免在分支指令之后执行流水线中剩余的任何指令。 流水线的冲洗通知指令获取控制机制，将指令流重定向到与固定地址对应的指令。 根据本发明的方法和装置进一步允许在发生分支指令中涉及的条件以外的条件时冲洗管道，例如冲洗陈旧的指令。