公开(公告)号：US06591360B1

公开(公告)日：2003-07-08

申请号：US09484138

申请日：2000-01-18

Applicant: Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Mark Gibson

Inventor： Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Mark Gibson

IPC: G06F930

CPC classification number: G06F9/3838 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3867

Abstract: A method and apparatus that generates a simplified, localized version (“a local stall”) of a global stall to improve the performance of a pipelined microprocessor. The local stall is generated when a data-dependency hazard is detected for a local consumer. Utilizing circuitry used in the pipelined microprocessor's data-forwarding circuitry, the local stall is generated with a relatively minor increase in circuitry. The local stall is generated much sooner than the global stall, arriving much sooner in a local pipeline. The local pipeline utilizes the local stall to override the global stall, when appropriate, and to ensure that correct data is read for a local consumer and to operate more efficiently than a standard pipeline without a local stall.

Abstract translation: 一种产生全局失速的简化的局部版本（“局部失速”）以改进流水线微处理器的性能的方法和装置。 当本地消费者检测到数据依赖性危险时，会产生本地摊位。 利用流水线微处理器的数据转发电路中使用的电路，产生局部失速，电路相对较小。 当地的摊位比全球摊位早得多，早在一个地方管道中就快到了。 当地管道利用本地摊位在适当的时候覆盖全局摊位，并确保为当地消费者读取正确的数据，并且比没有本地摊位的标准流水线更有效地运行。

公开(公告)号：US07213134B2

公开(公告)日：2007-05-01

申请号：US10092670

申请日：2002-03-06

Applicant: Donald C. Soltis, Jr. ,  Rohit Bhatia

Inventor： Donald C. Soltis, Jr. ,  Rohit Bhatia

IPC: G06F9/48

CPC classification number: G06F9/3851

Abstract: A processing unit of the invention has multiple instruction pipelines for processing multi-threaded instructions. Each thread may have an urgency associated with its program instructions. The processing unit has a thread switch controller to monitor processing of instructions through the various pipelines. The thread controller also controls switch events to move from one thread to another within the pipelines. The controller may modify the urgency of any thread such as by issuing an additional instruction. The thread controller preferably utilizes certain heuristics in making switch event decisions. A time slice expiration unit may also monitor expiration of threads for a given time slice.

Abstract translation: 本发明的处理单元具有用于处理多线程指令的多条指令流水线。 每个线程可能具有与其程序指令相关联的紧急性。 处理单元具有线程开关控制器，用于监视通过各种管线的指令处理。 线程控制器还控制开关事件在管道内从一个线程移动到另一个线程。 控制器可以通过发出附加指令来修改任何线程的紧急性。 螺纹控制器优选地在确定开关事件决定时利用某些启发式。 时间片过期单元还可以监视给定时间片的线程的到期时间。

公开(公告)号：US07930539B2

公开(公告)日：2011-04-19

申请号：US10910652

申请日：2004-08-03

Applicant: Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Eric R. DeLano

Inventor： Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Eric R. DeLano

IPC: H04L29/00 ,  G06F12/14 ,  G06F17/30

CPC classification number: G06F21/6281 ,  G06F2221/2105

Abstract: In a computer system including a plurality of resources, a device receives a request from a software program to access a specified one of the plurality of resources, determines whether the specified one of the plurality of resources is a protected resource. If the specified one of the plurality of resources is a protected resource, the device denies the request if the computer system is operating in a protected mode of operation, and processes the request based on access rights associated with the software program if the computer system is not operating in the protected mode of operation.

Abstract translation: 在包括多个资源的计算机系统中，设备接收来自软件程序的访问多个资源中指定的一个资源的请求，确定多个资源中指定的一个资源是否是受保护的资源。 如果多个资源中的指定的资源是受保护的资源，则如果计算机系统在受保护的操作模式下操作，则设备拒绝该请求，并且如果计算机系统是 不工作在受保护的操作模式。

公开(公告)号：US07421689B2

公开(公告)日：2008-09-02

申请号：US10695267

申请日：2003-10-28

Applicant: Jonathan K. Ross ,  Dale Morris ,  Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Eric Delano

Inventor： Jonathan K. Ross ,  Dale Morris ,  Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Eric Delano

IPC: G06F9/455

CPC classification number: G06F9/45533

Abstract: Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.

Abstract translation: 虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。 这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障， 尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

公开(公告)号：US09348766B2

公开(公告)日：2016-05-24

申请号：US13994690

申请日：2011-12-21

Applicant: Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

Inventor： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

IPC: G06F13/00 ,  G06F12/12 ,  G06F3/06 ,  G06F12/00 ,  G06F12/08

CPC classification number: G06F12/122 ,  G06F3/0604 ,  G06F12/00 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/124 ,  G06F12/125

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.

Abstract translation: 根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中，多个方式包括量是三的倍数而不是二的幂，并且其中多个方式被组织成多对。 在这种实施例中，装置还包括用于多个对中的每一对的单个比特，其中每个单个比特将用作表示相关联的一对路由的中间级别决策节点，以及具有正好两个单独比特的根级别决策节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。 还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

公开(公告)号：US09069690B2

公开(公告)日：2015-06-30

申请号：US13613777

申请日：2012-09-13

Applicant: Gur Hildesheim ,  Chang Kian Tan ,  Robert S. Chappell ,  Rohit Bhatia

Inventor： Gur Hildesheim ,  Chang Kian Tan ,  Robert S. Chappell ,  Rohit Bhatia

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/651 ,  G06F2212/655 ,  G06F2212/681 ,  G06F2212/684

Abstract: In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并且从寻呼结构获得物理地址的对应部分，与第一步行者并行操作的第二步行者，以及 用于防止第一步行器响应于匹配由第二步行者访问的并行寻呼结构的对应线性地址部分的第一线性地址部分而将所获得的物理地址部分存储在寻呼高速缓存器中的逻辑。 描述和要求保护其他实施例。

公开(公告)号：US08479029B2

公开(公告)日：2013-07-02

申请号：US13167970

申请日：2011-06-24

Applicant: Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

Inventor： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203

Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

公开(公告)号：US20110252255A1

公开(公告)日：2011-10-13

申请号：US13167970

申请日：2011-06-24

Applicant: Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

Inventor： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203

Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

Abstract translation: 公开了减少处理器的步进负载的方法和装置。 方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集 号码来控制执行期间的电量。 一些实施例还可以创建人为活动以为处理器提供最小功率层。 装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑 的执行期间要处理的指令。

公开(公告)号：US07992017B2

公开(公告)日：2011-08-02

申请号：US11900316

申请日：2007-09-11

Applicant: Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

Inventor： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

IPC: G06F1/32 ,  G06F11/30

CPC classification number: G06F1/3234 ,  G06F1/3203

Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

Abstract translation: 公开了减少处理器的步进负载的方法和装置。 方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并且将执行限制到指令的子集 号码来控制执行期间的电量。 一些实施例还可以创建人为活动以为处理器提供最小功率层。 装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑 的执行期间要处理的指令。

公开(公告)号：US20140181484A1

公开(公告)日：2014-06-26

申请号：US13725934

申请日：2012-12-21

Applicant: James Callister ,  Don Soltis ,  Rohit Bhatia ,  Ramkumar Srinivasan ,  Steven Bostian ,  Richard M. Blumberg

Inventor： James Callister ,  Don Soltis ,  Rohit Bhatia ,  Ramkumar Srinivasan ,  Steven Bostian ,  Richard M. Blumberg

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/4881

Abstract: According to one embodiment, a processor includes an execution pipeline for executing a plurality of threads, including a first thread and a second thread. The processor further includes a multi-thread controller (MTC) coupled to the execution pipeline to determine whether to switch threads between the first and second thread based on a thread switch policy that is selected from a list of thread switch policies based on unfairness levels of the first and second thread, and in response to determining to switch threads, to switch from executing the first thread to executing the second thread.

Abstract translation: 根据一个实施例，处理器包括用于执行包括第一线程和第二线程的多个线程的执行流水线。 处理器还包括耦合到执行流水线的多线程控制器（MTC），以基于从线程切换策略列表中选择的线程切换策略来确定是否在第一和第二线程之间切换线程，所述线程切换策略基于线程切换策略的列表， 第一线程和第二线程，并且响应于确定切换线程，从执行第一线程切换到执行第二线程。