公开(公告)号：US20140075123A1

公开(公告)日：2014-03-13

申请号：US13613777

申请日：2012-09-13

申请人： Gur HILDESHEIM ,  Chang Kian TAN ,  Robert S. CHAPPELL ,  Rohit BHATIA

发明人： Gur HILDESHEIM ,  Chang Kian TAN ,  Robert S. CHAPPELL ,  Rohit BHATIA

IPC分类号： G06F12/10

CPC分类号： G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/651 ,  G06F2212/655 ,  G06F2212/681 ,  G06F2212/684

摘要： In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并从寻呼结构获得物理地址的对应部分，与第一步行者同时操作的第二步行者， 逻辑，用于防止第一步行者将所获得的物理地址部分存储在响应于第一线性地址部分匹配第二步行者的并发寻呼结构访问的相应线性地址部分的寻呼高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US20150006834A1

公开(公告)日：2015-01-01

申请号：US13931875

申请日：2013-06-29

申请人： Subramanya R. DULLOOR ,  Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Richard A. UHLIG ,  Robert S. CHAPPELL ,  Joseph NUZMAN ,  Kai CHENG ,  Sailesh KOTTAPALLI ,  Yen-Cheng LIU ,  Mohan KUMAR ,  Raj K. RAMANUJAN ,  Glenn J. HINTON

发明人： Subramanya R. DULLOOR ,  Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Richard A. UHLIG ,  Robert S. CHAPPELL ,  Joseph NUZMAN ,  Kai CHENG ,  Sailesh KOTTAPALLI ,  Yen-Cheng LIU ,  Mohan KUMAR ,  Raj K. RAMANUJAN ,  Glenn J. HINTON

IPC分类号： G06F3/06

CPC分类号： G06F3/0604 ,  G06F3/0659 ,  G06F3/0671 ,  G06F13/1668

摘要： An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

摘要翻译： 描述了用于在持久存储器架构中的存储耐久性和排序的装置和方法。 例如，方法的一个实施例包括：对识别至少一个持久存储器设备的一个或多个地址执行至少一个存储操作，所述存储操作使一个或多个存储器控制器将数据存储在所述至少一个持久存储器设备中; 向所述一个或多个存储器控制器发送请求消息，指示所述存储器控制器确认所述存储操作被成功地提交给所述至少一个持久存储器设备; 确保在所述一个或多个存储器控制器处，至少在请求消息时接收到的所有未决存储操作将被提交给持久存储器设备; 以及从所述一个或多个存储器控制器发送指示所述存储操作被成功地提交给所述持久存储器设备的响应消息。

公开(公告)号：US20150006452A1

公开(公告)日：2015-01-01

申请号：US13931872

申请日：2013-06-29

申请人： Ho-Seop KIM ,  Robert S. CHAPPELL ,  Choon Yip SOO

发明人： Ho-Seop KIM ,  Robert S. CHAPPELL ,  Choon Yip SOO

IPC分类号： G06N5/04

CPC分类号： G06N5/04 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3855

摘要： An apparatus and method for store dependence prediction is described. For example, one embodiment of the invention includes a processor comprising a store buffer for buffering store operations prior to completion, the store operations to store data to a memory hierarchy; and a store dependence predictor to predict whether load operations should be permitted to speculatively skip over each store operation and responsively setting an indication within an entry associated with each store operation in the store buffer; wherein a load operation checks the indication in the store buffer to determine whether to speculatively execute ahead of each store operation.

摘要翻译： 描述了用于存储相关性预测的装置和方法。 例如，本发明的一个实施例包括处理器，其包括用于在完成之前缓存存储操作的存储缓冲器，用于将数据存储到存储器层次的存储操作; 以及存储相关预测器，用于预测是否允许加载操作被推测地跳过每个存储操作，并且响应地在与存储缓冲器中的每个存储操作相关联的条目内设置指示; 其中加载操作检查存储缓冲器中的指示以确定是否在每个存储操作之前推测地执行。