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    Integrated optical switch
    35.
    发明授权
    Integrated optical switch 有权

    公开(公告)号：US10972097B2

    公开(公告)日：2021-04-06

    申请号：US16643383

    申请日：2017-08-29

    Applicant: STMicroelectronics SA

    Inventor： Hanae Zegmout ,  Denis Pache ,  Stephane Le Tual ,  Jean-François Roux ,  Jean-Louis Coutaz

    IPC: H03K17/78 ,  H01L31/08 ,  H01L31/028 ,  H01L31/0352 ,  H03M1/12

    Abstract: In accordance with an embodiment of the present invention, an optical switch includes a photoconductor body including a first edge and an opposite second edge, a first end and an opposite second end. The first edge is configured to receive an electrical input signal and the second edge is configured to deliver an electrical output signal. The photoconductor body is configured to have an electrically ON state that is activated by an optical signal and an electrically OFF state that is activated by an absence of the optical signal. A direction from the first end to the second end defines a longitudinal direction. The direction from the first edge to the second edge defines a first direction that is orthogonal to the longitudinal direction. A first dimension between the first edge and the second edge along the first direction decreases from the first end to the second end.

    INTEGRATED CIRCUIT WITH DOUBLE ISOLATION OF DEEP AND SHALLOW TRENCH-ISOLATION TYPE
    36.
    发明申请
    INTEGRATED CIRCUIT WITH DOUBLE ISOLATION OF DEEP AND SHALLOW TRENCH-ISOLATION TYPE 有权

    公开(公告)号：US20210020660A1

    公开(公告)日：2021-01-21

    申请号：US16927510

    申请日：2020-07-13

    Applicant: STMicroelectronics SA

    Inventor： Thomas BEDECARRATS ,  Philippe GALY

    IPC: H01L27/12

    Abstract: A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.

    DATA TRANSMISSION, IN PARTICULAR ON A SERIAL LINK HAVING A GREAT LENGTH
    38.
    发明申请
    DATA TRANSMISSION, IN PARTICULAR ON A SERIAL LINK HAVING A GREAT LENGTH 审中-公开

    公开(公告)号：US20200373965A1

    公开(公告)日：2020-11-26

    申请号：US16878084

    申请日：2020-05-19

    Applicant: STMicroelectronics SA

    Inventor： Mohammed TMIMI ,  Philippe GALY

    IPC: H04B3/02 ,  H04L27/20

    Abstract: Binary data is processed through a differential pre-encoder, which includes a simple modulo-2 addition. This step is used to cancel the propagation error that can be introduced by duo-binary modulation and to simplify demodulation. Next the duo-binary encoder introduces controlled Inter Symbol Interference between a previously sent bit and a present bit to compress the spectral density closer to the DC. Next a 60-GHz carrier is modulated and transmitted over differential transmission lines.

    METHOD AND DEVICE FOR CALIBRATING A HYBRID COUPLER
    39.
    发明申请
    METHOD AND DEVICE FOR CALIBRATING A HYBRID COUPLER 审中-公开

    公开(公告)号：US20200350653A1

    公开(公告)日：2020-11-05

    申请号：US16764947

    申请日：2017-11-21

    Applicant: STMicroelectronics SA

    Inventor： Vincent KNOPIK ,  Jeremie FOREST ,  Eric KERHERVE

    IPC: H01P5/22 ,  H04B17/21 ,  H01L23/522 ,  H03H11/16

    Abstract: A hybrid coupler operating in a power divider mode includes two inputs, two outputs, a capacitive module coupled between the inputs and the outputs or on each input and each output. The capacitive module has an adjustable capacitive value making it possible to adjust the central frequency. A calibration method includes: delivering a first reference signal having a first reference frequency on the first input of the hybrid coupler, measuring the peak value of a first signal delivered to the first output of the coupler and measuring the peak value of a second signal delivered to the second output of the coupler. The two peak values are compared and an adjustment of the capacitive value of the capacitive module is made until an equality of the peak values is obtained to within a tolerance.

    Flip-flop with a metal programmable initialization logic state
    40.
    发明授权
    Flip-flop with a metal programmable initialization logic state 有权

    公开(公告)号：US10804885B2

    公开(公告)日：2020-10-13

    申请号：US16654261

    申请日：2019-10-16

    Applicant: STMicroelectronics SA

    Inventor： Sylvain Engels ,  Alain Aurand ,  Etienne Maurin

    IPC: H03K3/00 ,  H03K3/356 ,  H01L27/02 ,  H03K3/3562 ,  H03K19/0948 ,  H01L23/528

    Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).

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