公开(公告)号：US20250167141A1

公开(公告)日：2025-05-22

申请号：US18735927

申请日：2024-06-06

Applicant: SAMSUNG ELECTRONICS, CO., LTD.

Inventor： YoungJun KIM ,  Sangjine Park ,  Jinmyoung Lee

IPC: H01L23/64 ,  H01L21/764 ,  H01L23/528 ,  H01L29/417

Abstract: A semiconductor device includes a base insulation layer including a first surface and a second surface facing the first surface, a channel layer on the first surface of the base insulation layer, source/drain patterns disposed in a first direction parallel to the first surface of the base insulation layer interposing the channel layer, a gate structure extending in a second direction crossing the first direction on the first surface of the base insulation layer and at least partially surrounding the channel layer, a gate separation pattern crossing the gate structure and at least partially penetrating the gate structure in a third direction perpendicular to the first direction and the second direction, and a through electrode at least partially penetrating the gate separation pattern in the third direction.

公开(公告)号：US20250167135A1

公开(公告)日：2025-05-22

申请号：US18749785

申请日：2024-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongkook Kim ,  Heungkyu Kwon ,  Junghwan Jang ,  Youngcheol Kim ,  Choonheung Lee ,  Minki Ahn ,  Jaegwon Jang ,  Hangchul Choi ,  Heejung Choi

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/49 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16

Abstract: A semiconductor package including a first redistribution structure, a second redistribution structure disposed on the first redistribution structure, a semiconductor chip disposed on an upper surface of the second redistribution structure, a bridge chip disposed on a lower surface of the second redistribution structure, a molding layer disposed between the first redistribution structure and the second redistribution structure, where the molding layer surrounds the bridge chip, and a stiffener disposed on the upper surface of the second redistribution structure. The stiffener includes an opening. The semiconductor chip is disposed in the opening of the stiffener.

公开(公告)号：US20250167134A1

公开(公告)日：2025-05-22

申请号：US18646294

申请日：2024-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huishu MA

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: Provided is a semiconductor package structure including a substrate, a plurality of chips on the substrate in a second direction perpendicular to a surface of the substrate, a plurality of bonding wires connecting the plurality of chips to bonding pads included in the substrate, respectively, and a molding layer on the substrate, the molding layer encapsulating the plurality of chips and the plurality of bonding wires, wherein at least one first chip of the plurality of chips includes an overhanging portion protruding with respect to a second chip of the plurality of chips on the at least one first chip in a first direction parallel to the surface of the substrate, and wherein a support is on the at least one first chip.

公开(公告)号：US20250167133A1

公开(公告)日：2025-05-22

申请号：US19029292

申请日：2025-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngwoo PARK

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The method inluces forming a semiconductor chip, forming an electromagnetic shield that covers the semiconductor chip, and forming a molding that covers the electromagnetic shield. The electromagnetic shield is electrically connected to a conductor on a side of the semiconductor chip.

公开(公告)号：US20250167087A1

公开(公告)日：2025-05-22

申请号：US18775998

申请日：2024-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dowan Kim ,  Seung Hun Chae ,  Un-Byoung Kang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor package includes a wiring substrate that includes a wiring pattern, a dielectric pattern that covers the wiring pattern, a substrate pad on the dielectric pattern and including a recess that extends from a top surface of the substrate pad toward an inside of the substrate pad, a metal layer on a bottom surface of the recess and spaced apart from an inner lateral surface of the recess, and a protection layer on the dielectric pattern and covering the substrate pad. The substrate pad penetrates the dielectric pattern to come into connection with the wiring pattern. The protection layer exposes at least a portion of the metal layer. The protection layer extends from the top surface of the substrate pad to fill a space between a lateral surface of the metal layer and the inner lateral surface of the recess.

公开(公告)号：US20250167061A1

公开(公告)日：2025-05-22

申请号：US19029411

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

公开(公告)号：US20250167056A1

公开(公告)日：2025-05-22

申请号：US18744964

申请日：2024-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuhyeong KIM ,  Chaein MOON

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/36 ,  H01L23/498

Abstract: Provided is a semiconductor package including a substrate defining a first recess portion and a plurality of second recess portions, the plurality of second recess portions are arranged on a bottom surface of the first recess portion, a semiconductor chip in the first recess portion of the substrate, solder balls arranged in the plurality of second recess portions of the substrate and electrically connected to the semiconductor chip, and a heat dissipation structure on the substrate and the semiconductor chip, the bottom surface of the first recess portion of the substrate being on a higher level than upper surfaces of the solder balls.

公开(公告)号：US20250167054A1

公开(公告)日：2025-05-22

申请号：US18675860

申请日：2024-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DUCKGYU KIM

IPC: H01L21/66 ,  H01L23/544

Abstract: Disclosed are semiconductor chips and semiconductor packages including the same. The semiconductor chip comprises a substrate that includes a device region and an edge region, a conductive pad on the device region of the substrate, a residual test pattern on the edge region of the substrate, and a redistribution layer on the substrate and covering the conductive pad. The redistribution layer includes a first dielectric layer and a second dielectric layer. The residual test pattern includes a pattern cut part that has a lateral surface aligned with that of the substrate, and a pattern edge part between the pattern cut part and the conductive pad. The first dielectric layer entirely covers the pattern edge part and partially covers the pattern cut part. There is a step difference between sidewalls of the first and second dielectric layers such that the second dielectric layer does not cover the residual test pattern.

公开(公告)号：US20250167031A1

公开(公告)日：2025-05-22

申请号：US18890154

申请日：2024-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hosin SONG ,  Yeongkwon KO ,  Jiyoung PARK ,  Junyeong HEO

IPC: H01L21/683 ,  H01L21/304 ,  H01L21/66 ,  H01L21/68

Abstract: A carrier substrate according to some example embodiments is a carrier substrate having a circular disk shape, and includes a first surface, a second surface opposite surface to first surface, and an inclined surface that extends along the edge of the first surface, has an inclination angle from the first surface, and is configured to reflect incident light from the second surface.

公开(公告)号：US20250167015A1

公开(公告)日：2025-05-22

申请号：US18668361

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donguk KWON

IPC: H01L21/67 ,  H01L21/60 ,  H01L21/603 ,  H01L21/683 ,  H01L23/00

Abstract: The inventive concept relates to an apparatus for manufacturing a semiconductor package and a method of manufacturing a semiconductor package. According to embodiments, the method of manufacturing a semiconductor package may include preparing a substrate including upper conductive pads on an upper surface of the substrate, preparing a first semiconductor chip including first solder balls, wherein a first dielectric layer covering sidewalls of the first solder balls is on a lower surface of the first semiconductor chip, disposing the first semiconductor chip on the substrate such that the first solder balls are on the upper conductive pads, and bonding the first solder balls to the upper conductive pads by applying an alternating current electric field to the first dielectric layer.