公开(公告)号：US07157342B1

公开(公告)日：2007-01-02

申请号：US11026400

申请日：2004-12-29

Applicant: Marc Tarabbia ,  Scott Robins

Inventor： Marc Tarabbia ,  Scott Robins

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/7436

Abstract: A thyristor-based memory device may comprise a commonly-implanted base region, in which a common emitter region may be implanted for the left and the right thyristors in a mirror-image pair. The implanting of the base region may include directing the dopant toward a semiconductor material through a window defined by sidewalls formed in a conditioned masking material over the semiconductor material. The resulting base and emitter regions may be substantially symmetrical about a central boundary plane. In relation to the symmetry, one thyristor may be operable with a minimum holding current within about 10 percent of that for the other thyristor in the mirror-image pair.

Abstract translation: 基于晶闸管的存储器件可以包括共同植入的基极区域，其中可以以镜像对为左和右晶闸管注入公共发射极区域。 基极区域的注入可以包括通过半导体材料上经调节的掩蔽材料形成的侧壁限定的窗口来引导掺杂剂朝向半导体材料。 所得到的基极和发射极区域可以基本上关于中心边界平面对称。 关于对称性，一个晶闸管可以以最小的保持电流工作，在镜像对中的另一个晶闸管的约10％的范围内。

公开(公告)号：US07135745B1

公开(公告)日：2006-11-14

申请号：US10238572

申请日：2002-09-09

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L29/72

CPC classification number: H01L29/7436 ,  H01L27/1027 ,  H01L29/87

Abstract: A semiconductor device having a thyristor-based device and a pass device exhibits characteristics that may include, for example, resistance to short channel effects that occur when conventional MOSFET devices are scaled smaller in connection with advancing technology. According to an example embodiment of the present invention, the semiconductor device includes a pass device having a channel in a fin portion over a semiconductor substrate, and a thyristor device coupled to the pass device. The fin has a top portion and a side portion and extends over the semiconductor substrate. The pass device includes source/drain regions separated by the channel and a gate facing and capacitively coupled to the side portion of the fin that includes the channel. The thyristor device includes anode and cathode end portions, each end portion having base and emitter regions, where one of the emitter regions is coupled to one of the source/drain regions of the pass device. The gate of the pass device is further adapted to switch the pass device between a blocking state and a conducting state via the capacitive coupling and form a conductive path between the source/drain regions. A control port is capacitively coupled to the base region of the end portion of the thyristor that is coupled to the source/drain region of the pass gate and is adapted to facilitate switching of the thyristor between blocking and conducting states.

Abstract translation: 具有基于晶闸管的器件和通过器件的半导体器件表现出特性，其可以包括例如当传统MOSFET器件与前进技术相比缩小时发生的短沟道效应的阻力。 根据本发明的示例实施例，半导体器件包括通过器件，其具有在半导体衬底上的鳍部分中的沟道，以及耦合到通过器件的晶闸管器件。 翅片具有顶部和侧部并且在半导体衬底上延伸。 通过装置包括由通道分离的源极/漏极区域和面对并电容耦合到包括通道的鳍片的侧部的门。 晶闸管器件包括阳极和阴极端部，每个端部具有基极和发射极区域，其中发射极区域之一耦合到通过器件的源极/漏极区域之一。 通过装置的栅极还适于经由电容耦合在阻塞状态和导通状态之间切换通过装置，并在源/漏区之间形成导电路径。 控制端口电容耦合到晶闸管的端部的基极区域，该基极区域耦合到栅极的源极/漏极区域并且适于促进晶闸管在阻塞和导通状态之间的切换。

公开(公告)号：US07064977B1

公开(公告)日：2006-06-20

申请号：US11134004

申请日：2005-05-20

Applicant: Andrew Horch ,  Tapan Samaddar ,  Scott Robins

Inventor： Andrew Horch ,  Tapan Samaddar ,  Scott Robins

IPC: G11C7/00

CPC classification number: G11C7/14

Abstract: A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the reference current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cells' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half of the current from the memory cell. The reference voltage is then applied to other reference cells in a memory array.

公开(公告)号：US06979602B1

公开(公告)日：2005-12-27

申请号：US10730755

申请日：2003-12-08

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L21/762 ,  H01L27/08 ,  H01L29/74 ,  H01L21/332

CPC classification number: H01L21/76224 ,  H01L27/0817 ,  H01L29/74

Abstract: A semiconductor device is formed including a substrate having an upper surface, a thyristor region in the substrate and a control port adapted for capacitively coupling to at least a portion of the thyristor region via a dielectric material. According to an example embodiment of the present invention, a trench is formed in the substrate and subsequently filled with materials including dielectric material and a control port. The control port is adapted for capacitively coupling to the thyristor via the dielectric material for controlling current flow in the thyristor (e.g., for causing an outflow of minority carriers from a portion of the thyristor for switching the thyristor from conducting state to a blocking state). A portion of the substrate adjacent to the upper surface is implanted with a species of ions, and the dielectric material via which the control port capacitively couples to the thyristor does not include the species of ions. In one implementation, a filled portion of the trench over the control port inhibits ions from implanting the dielectric material. In another implementation, the control port is formed recessed, relative to the upper surface of the substrate, such that the ion implant depth of the region adjacent to the upper surface is shallower than the recessed control port. With this approach, current control in the thyristor is effected using an arrangement that inhibits ion implantation damage to dielectric material used for controlling current in the thyristor.

Abstract translation: 形成半导体器件，其包括具有上表面的衬底，衬底中的晶闸管区域和适于经由电介质材料电容耦合到晶闸管区域的至少一部分的控制端口。 根据本发明的示例性实施例，在衬底中形成沟槽，随后填充包括电介质材料和控制端口的材料。 控制端口适于通过用于控制晶闸管中的电流的电介质材料电容耦合到晶闸管（例如，用于使晶闸管的一部分的少数载流子流出，将晶闸管从导通状态切换到阻塞状态） 。 与上表面相邻的衬底的一部分注入一些离子，并且电容耦合到晶闸管的电介质材料不包括离子种类。 在一个实施方案中，控制端口上的沟槽的填充部分抑制离子注入电介质材料。 在另一实施方案中，控制端口相对于衬底的上表面形成为凹陷，使得与上表面相邻的区域的离子注入深度比凹入的控制端口浅。 采用这种方法，晶闸管的电流控制是通过抑制用于控制晶闸管中的电流的电介质材料的离子注入损伤的装置实现的。

公开(公告)号：US06944051B1

公开(公告)日：2005-09-13

申请号：US10695171

申请日：2003-10-29

Applicant: Zachary K. Lee ,  Farid Nemati ,  Scott Robins

Inventor： Zachary K. Lee ,  Farid Nemati ,  Scott Robins

IPC: G11C11/00

CPC classification number: G11C11/39

Abstract: In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, the second end is pulled down to zero or even a negative value. If the cell is storing a “1,” the voltage at the thyristor cathode can be approximately 0.6 volt at the time of the pull down. The large forward-bias across the diode pulls down the thryistor cathode. This causes the thyristor to be restored. If the cell is storing a “0,” the voltage at the thyristor cathode can be approximately zero volt. The small or zero forward-bias across the diode is unable to disturb the “0” state. As a result, the memory cell is restored to its original state.

Abstract translation: 在基于晶闸管的存储单元中，反向偏置二极管的一端连接到晶闸管的阴极。 在待机期间，二极管的第二端被偏置在高于晶闸管阴极处的电压。 在恢复操作期间，第二端被拉低至零或甚至负值。 如果电池正在存储“1”，则在下拉时，晶闸管阴极处的电压可能约为0.6伏特。 二极管两端的大正向偏置可降低晶闸管阴极。 这导致晶闸管恢复。 如果电池正在存储“0”，晶闸管阴极处的电压可以近似为零伏。 二极管两端的小或零正向偏置不能干扰“0”状态。 结果，存储单元恢复到其原始状态。

公开(公告)号：US06872602B1

公开(公告)日：2005-03-29

申请号：US10785166

申请日：2004-02-23

Applicant: Farid Nemati ,  Badredin Fatemizadeh ,  Andrew Horch ,  Scott Robins

Inventor： Farid Nemati ,  Badredin Fatemizadeh ,  Andrew Horch ,  Scott Robins

IPC: H01L21/8242 ,  H01L21/8244 ,  H01L27/08 ,  H01L27/108 ,  H01L27/11 ,  H01L29/417 ,  H01L29/74 ,  H01L21/332

CPC classification number: H01L29/41716 ,  H01L27/0817 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11 ,  H01L29/74

Abstract: Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

Abstract translation: 通过增强从掩埋晶闸管 - 发射极区域的载流子排放，可以改善晶闸管基半导体器件的开关时间。 根据本发明的示例性实施例，导电接触延伸到掩埋在衬底中的掺杂阱区，并且适于从其引出载流子。 该器件包括晶体管本体，其具有埋在掺杂阱区中的至少一个掺杂射极区。 导电晶闸管控制端口适于电容耦合到晶闸管主体并控制其中的电流。 通过这种方法，晶闸管可以在电阻状态之间快速切换，这已经被发现在包括但不限于存储器单元应用的高速数据锁存实现中特别有用。

公开(公告)号：US06828176B1

公开(公告)日：2004-12-07

申请号：US10650334

申请日：2003-08-28

Applicant: Farid Nemati ,  Scott Robins ,  Andrew Horch

Inventor： Farid Nemati ,  Scott Robins ,  Andrew Horch

IPC: H01L21332

CPC classification number: G11C11/39 ,  H01L27/1203 ,  H01L29/0834 ,  H01L29/41725 ,  H01L29/7436

Abstract: A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.

Abstract translation: 基于晶闸管的半导体器件表现出相对增加的基极 - 发射极电容。 根据本发明的示例性实施例，晶闸管的基极区域和相邻发射极区域被掺杂，使得发射极区域相对于基极区域具有光掺杂剂浓度的轻掺杂部分。 在一个实施例中，晶闸管实现在存储器电路中，其中发射极区域耦合到参考电压线，并且控制端口布置成电容耦合到晶闸管以控制其中的电流流动。 在另一实施方案中，晶闸管形成在绝缘体上硅（SOI）结构的掩埋绝缘体层上。 利用这些方法，可以严格控制晶闸管中的电流，例如用于数据存储在其中。

公开(公告)号：US06727528B1

公开(公告)日：2004-04-27

申请号：US09815213

申请日：2001-03-22

Applicant: Scott Robins ,  Andrew Horch ,  Farid Nemati ,  Hyun-Jin Cho

Inventor： Scott Robins ,  Andrew Horch ,  Farid Nemati ,  Hyun-Jin Cho

IPC: H01L2974

CPC classification number: H01L29/66363 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/763 ,  H01L27/0617 ,  H01L27/0817

Abstract: A semiconductor device includes a thyristor designed to reduce or eliminate manufacturing and operational difficulties commonly experienced in the formation and operation of NDR devices. According to one example embodiment of the present invention, the semiconductor substrate is trenched adjacent a doped or dopable substrate region, which is formed to include at least two vertically-adjacent thyristor regions of different polarity. A capacitively-coupled control port for the thyristor is coupled to at least one of the thyristor regions. The trench also includes a dielectric material for electrically insulating the vertically-adjacent thyristor regions. The thyristor is electrically connected to other circuitry in the device, such as a transistor, and used to form a device, such as a memory cell.

Abstract translation: 半导体器件包括设计用于减少或消除在NDR器件的形成和操作中通常经历的制造和操作困难的晶闸管。 根据本发明的一个示例性实施例，半导体衬底在掺杂或可掺杂的衬底区域附近被沟槽，该衬底区域被形成为包括具有不同极性的至少两个垂直相邻的晶闸管区域。 用于晶闸管的电容耦合控制端口耦合到至少一个晶闸管区域。 沟槽还包括用于使垂直相邻的晶闸管区域电绝缘的电介质材料。 晶闸管电连接到器件中的其它电路，例如晶体管，并用于形成诸如存储器单元的器件。

公开(公告)号：US06703646B1

公开(公告)日：2004-03-09

申请号：US10253363

申请日：2002-09-24

Applicant: Farid Nemati ,  Scott Robins ,  Andrew Horch

Inventor： Farid Nemati ,  Scott Robins ,  Andrew Horch

IPC: H01L2974

CPC classification number: G11C11/39 ,  H01L27/1203 ,  H01L29/0834 ,  H01L29/41725 ,  H01L29/7436

Abstract: A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.

Abstract translation: 基于晶闸管的半导体器件表现出相对增加的基极 - 发射极电容。 根据本发明的示例性实施例，晶闸管的基极区域和相邻发射极区域被掺杂，使得发射极区域相对于基极区域具有光掺杂剂浓度的轻掺杂部分。 在一个实施例中，晶闸管实现在存储器电路中，其中发射极区域耦合到参考电压线，并且控制端口布置成电容耦合到晶闸管以控制其中的电流流动。 在另一实施方案中，晶闸管形成在绝缘体上硅（SOI）结构的掩埋绝缘体层上。 利用这些方法，可以严格控制晶闸管中的电流，例如用于数据存储在其中。

公开(公告)号：US06462359B1

公开(公告)日：2002-10-08

申请号：US09814980

申请日：2001-03-22

Applicant: Farid Nemati ,  Hyun-Jin Cho ,  Scott Robins

Inventor： Farid Nemati ,  Hyun-Jin Cho ,  Scott Robins

IPC: H01L2974

CPC classification number: G11C11/39 ,  H01L29/7436 ,  H01L29/749

Abstract: A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt between a base and emitter region in a thyristor that effects a leakage current in the thyristor. The thyristor includes a capacitively coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region, and the current shunt is located between the emitter and base region of one of the end portions of the thyristor. The current shunt is configured and arranged to shunt low-level current between the emitter region and the adjacent base region, and in doing so improves the ability of the device to operate under adverse conditions that would, absent the shunt, result in inadvertent turn on, while keeping the standby current of the memory device to an acceptably low level.

Abstract translation: 具有基于晶闸管的存储器件的半导体器件在与温度，噪声，电扰动和光线相关的不利操作条件下表现出改进的稳定性。 在本发明的一个具体示例性实施例中，半导体器件包括基于晶闸管的存储器件，其使用晶闸管中的基极和发射极区之间的分流器，其实现晶闸管中的漏电流。 晶闸管包括电容耦合的控制端口和阳极和阴极端部分。 每个端部具有发射极区域和相邻的基极区域，并且电流分流器位于晶闸管的一个端部的发射极和基极区域之间。 电流分流器被配置和布置成在发射极区域和相邻基极区域之间分流低电平电流，并且在这样做时改善了器件在不利条件下操作的能力，这在不存在分流的情况下导致无意中导通 同时将存储器件的待机电流保持在可接受的低电平。