公开(公告)号：US06790539B2

公开(公告)日：2004-09-14

申请号：US10197825

申请日：2002-07-19

申请人： Tung-Shen Lin

发明人： Tung-Shen Lin

IPC分类号： H05B3312

CPC分类号： H05B33/14 ,  C09K11/06 ,  C09K2211/1037 ,  H01L51/0052 ,  H01L51/0059 ,  H01L51/0071 ,  H01L51/0072 ,  H01L51/0081 ,  H01L2251/308 ,  Y10S428/917

摘要： An organic EL device which contains an anode, a cathode, and at least one organic thin-film layer including a light emitting layer which contains a compound represented by the following general formula (1): wherein Ar1, Ar2 represent a substituted or unsubstituted aromatic hydrocarbon group, or a substituted or unsubstituted aromatic heterocyclic group; Y represents a single bond or —CH═CH— group; R1 to R4 represent each independently a hydrogen, a halogen, a cyano group, a substituted amino group, a substituted alkoxy group, a substituted or unsubstituted alkyl group, a substituted or unsubstituted aromatic hydrocarbon group, or a substituted or unsubstituted aromatic heterocyclic group; any two of R1 to R4 may form a ring; R5 represents a substituted or unsubstituted alkyl group, a substituted or unsubstituted aromatic hydrocarbon group, or a substituted or unsubstituted aromatic heterocyclic group.

摘要翻译： 一种含有阳极，阴极和至少一个有机薄膜层的有机EL器件，包括含有下述通式（1）表示的化合物的发光层：其中Ar1，Ar2表示取代或未取代的芳族 烃基或取代或未取代的芳族杂环基; Y表示单键或-CH = CH-基团; R 1〜R 4各自独立地表示氢，卤素，氰基，取代氨基，取代烷氧基，取代或未取代的烷基，取代或未取代的芳香族烃基或取代或未取代的芳香族杂环基。 R1至R4中的任何两个可以形成环; R 5表示取代或未取代的烷基，取代或未取代的芳香族烃基或取代或未取代的芳香族杂环基。

公开(公告)号：USD479950S1

公开(公告)日：2003-09-30

申请号：US29159457

申请日：2002-04-23

申请人： Shyn-Shen Lin

设计人： Shyn-Shen Lin

公开(公告)号：US06566924B2

公开(公告)日：2003-05-20

申请号：US09911398

申请日：2001-07-25

申请人： Shen Lin ,  Norman Chang ,  Keunmyung Lee ,  Osamu Nakagawa ,  Weize Xie

发明人： Shen Lin ,  Norman Chang ,  Keunmyung Lee ,  Osamu Nakagawa ,  Weize Xie

IPC分类号： H03L700

CPC分类号： H03L7/00 ,  G06F1/10

摘要： A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.

公开(公告)号：US06546576B1

公开(公告)日：2003-04-15

申请号：US09985509

申请日：2001-11-05

申请人： Ku-Shen Lin

发明人： Ku-Shen Lin

IPC分类号： H47C2104

CPC分类号： A47C21/048 ,  A47C21/044

摘要： An improved structure of a ventilated mattress with cooling and warming effect is disclosed. The structure comprises a mattress body, a warming/cooling air-delivery controlling box, and a connecting tube. The control box produces warming/cooling air to the mattress body via the connecting tube and the warming/cooling air is released via a plurality of ventilation buttons mounted at the surface of the mattress body. Thereby, the mattress provides the user with a warming/cooling effect.

摘要翻译： 公开了具有冷却和加温效果的通风床垫的改进结构。 该结构包括床垫体，加温/冷却送风控制箱和连接管。 控制箱通过连接管产生加热/冷却空​​气到床垫本体，并且加温/冷却空气通过安装在床垫主体表面的多个通风按钮释放。 因此，床垫向使用者提供加温/冷却效果。

公开(公告)号：US06434724B1

公开(公告)日：2002-08-13

申请号：US09531093

申请日：2000-03-18

申请人： Norman H. Chang ,  Shen Lin ,  O. Samual Nakagawa

发明人： Norman H. Chang ,  Shen Lin ,  O. Samual Nakagawa

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method of operating a data processing system to estimate the inductance values associated with a first metal trace having a defined width, thickness, and length in an integrated circuit. In the present invention, the number and location of any ground planes that are adjacent to the first trace in the integrated circuit are first determined. A first current loop passing through the first trace that depends on the number and location of the ground planes, if any, is defined. The magnetic flux per unit area generated in the first current loop when a predetermined current passes through the first trace is then determined and used to estimate the self-inductance of the first trace. If the first trace is adjacent to any ground planes, current loops through the first trace and the ground planes are also defined. The mutual inductance of the first trace and a second trace parallel thereto is determined by defining a current loop that passes through the first and second traces and determining the magnetic flux per unit area generated in the current loop when a predetermined current flows through the first trace. If the first trace and the second trace are adjacent to ground planes, additional current loops passing through each ground plane and one of the first and second traces are also defined. The invention reduces the computational workload inherent in extracting inductance by substituting N two-trace problems for the general problem involving N parallel traces.

摘要翻译： 一种操作数据处理系统以估计与集成电路中具有限定的宽度，厚度和长度的第一金属迹线相关联的电感值的方法。 在本发明中，首先确定与集成电路中的第一迹线相邻的任何接地层的数量和位置。 定义通过第一迹线的第一个电流环，其取决于接地平面的数量和位置（如果有的话）。 然后确定当预定电流通过第一迹线时在第一电流回路中产生的每单位面积的磁通量，并用于估计第一迹线的自感。 如果第一条迹线与任何接地平面相邻，则还定义了通过第一迹线和接地平面的电流回路。 通过限定通过第一和第二迹线的电流回路来确定第一迹线和与其平行的第二迹线的互感，并且当预定电流流过第一迹线时确定在电流回路中产生的每单位面积的磁通量 。 如果第一迹线和第二迹线与接地层相邻，则还定义了通过每个接地平面以及第一和第二迹线之一的额外电流回路。 本发明通过将N个二维问题替换为涉及N个并行轨迹的一般问题来减少提取电感所需的计算量。

公开(公告)号：US06359136B1

公开(公告)日：2002-03-19

申请号：US09716605

申请日：2000-11-20

申请人： Jolie Ann Bastian ,  Matthew Joseph Fisher ,  Richard Waltz Harper ,  Ho-Shen Lin ,  Jefferson Ray McCowan ,  Daniel Jon Sall ,  Gerald Floyd Smith ,  Kumiko Takeuchi ,  Michael Robert Wiley ,  Minsheng Zhang

发明人： Jolie Ann Bastian ,  Matthew Joseph Fisher ,  Richard Waltz Harper ,  Ho-Shen Lin ,  Jefferson Ray McCowan ,  Daniel Jon Sall ,  Gerald Floyd Smith ,  Kumiko Takeuchi ,  Michael Robert Wiley ,  Minsheng Zhang

IPC分类号： C07D47104

CPC分类号： C07D471/04

摘要： This application relates to novel compounds of formula I (and their pharmaceutically acceptable salts), as defined herein, processes and intermediates for their preparation, pharmaceutical formulations comprising the novel compounds of formula I, and the use of the compounds of formula I as thrombin inhibitors.

摘要翻译： 本申请涉及本文定义的式I（及其药学上可接受的盐）的新型化合物，其制备方法和中间体，包含式I的新型化合物的药物制剂以及式I化合物作为凝血酶抑制剂的用途 。

公开(公告)号：US06350883B1

公开(公告)日：2002-02-26

申请号：US09721285

申请日：2000-11-22

申请人： Shien-Chang Chen ,  Fu-Shen Lin ,  Liang-An Hsu ,  Cheng-Lin Tsai ,  Joe-Min Lin

发明人： Shien-Chang Chen ,  Fu-Shen Lin ,  Liang-An Hsu ,  Cheng-Lin Tsai ,  Joe-Min Lin

IPC分类号： C07D207267

CPC分类号： C07D207/267 ,  C07D201/08

摘要： The present invention is related to a method for preparing lactam represented by the following formula: wherein R is C2-10 alkylene which may be optionally substituted with C1-6 alkyl or phenyl; R′ is a hydrogen atom, C1-6 alkyl, C1-6 hydroxyalkyl or phenyl. The method for preparing lactam comprises an amination reaction using crystalline aluminosilicate zeolites as catalysts under the condition of gas phase in the presence of (a) lactone, (b) amine and/or ammonia and (c) water.

摘要翻译： 本发明涉及一种由下式表示的制备内酰胺的方法：其中R是可被C1-6烷基或苯基任意取代的C 2-10亚烷基; R'是氢原子，C 1-6烷基，C 1-6羟基烷基或苯基。 制备内酰胺的方法包括在（a）内酯，（b）胺和/或氨和（c）水的存在下，在气相条件下使用结晶硅铝酸盐沸石作为催化剂的胺化反应。

公开(公告)号：US06323347B2

公开(公告)日：2001-11-27

申请号：US09737894

申请日：2000-12-15

申请人： Shien-Chang Chen ,  Fu-Shen Lin ,  Liang-An Hsu ,  Cheng-Lin Tsai

发明人： Shien-Chang Chen ,  Fu-Shen Lin ,  Liang-An Hsu ,  Cheng-Lin Tsai

IPC分类号： C07D30732

CPC分类号： C07D315/00 ,  B01J23/78 ,  B01J23/80

摘要： The present invention relates to a catalyst for preparing a lactone, which is prepared by supporting a cupric compound, a zinc compound and at least one alkaline earth metal compound on the supporter. The present invention also relates to a method for preparing a lactone, which comprises a dehydrocyclization reaction of a diol under a gas phase in the presence of the aforementioned catalyst after activating said catalyst. The catalyst for preparing lactone of the present invention is quite economic because of its high activity, long lifetime and high selectivity of products.

公开(公告)号：US06189724B1

公开(公告)日：2001-02-20

申请号：US09520182

申请日：2000-03-07

申请人： Shyn-Shen Lin

发明人： Shyn-Shen Lin

IPC分类号： B65D2540

CPC分类号： B65D1/40 ,  A47G19/2261 ,  B29C45/16 ,  B29L2031/712

摘要： A container has a container body formed with horizontal and vertical grooves and square cone-shaped recessed separated by the grooves in an outer surface by a first injection process. Then the container body has slide-resistant decorations of soft material filled in the grooves and the recesses as integral in a second injecting process. The bottom of the container body also has a circular recess and a number of radial grooves extending out of the circular recess and filled with slide-resistant decorations. Then the container can be tightly held manually and stand on the surface of a table stabilized by means of the slide-resistant decorations.

摘要翻译： 容器具有形成有水平和垂直凹槽的容器主体和通过第一注射过程在外表面中被凹槽分隔的方锥形凹部。 然后，容器主体在第二次注射过程中将填充在槽和凹部中的软质材料具有防滑装饰。 容器主体的底部还具有圆形凹槽和从圆形凹槽延伸出来的多个径向凹槽并且填充有防滑装饰物。 然后容器可以手动紧固，并站立在通过防滑装置稳定的桌子的表面上。

公开(公告)号：US6021083A

公开(公告)日：2000-02-01

申请号：US051005

申请日：1998-03-30

申请人： Tzeng-Huei Shiau ,  Yu-Shen Lin ,  Ray-Lin Wan

发明人： Tzeng-Huei Shiau ,  Yu-Shen Lin ,  Ray-Lin Wan

IPC分类号： G11C8/08 ,  G11C16/08 ,  G11C13/00

CPC分类号： G11C8/08 ,  G11C16/08

摘要： The negative supply voltage used by the drivers during sector or chip level erase operations is decoded separately from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, and a set of wordline drivers. The wordline drivers are coupled to the first and second supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors. Each supply voltage selector in the set is coupled with a subset of the set of drivers. The subset of drivers is coupled with a respective segment in the array. The supply voltage selectors select a negative erase supply voltage or an erase inhibit supply voltage during an erase mode in response to address signals identifying the respective segments. The selected negative erase supply voltage or erase inhibit supply voltage is applied to the subsets of the set of drivers which are coupled to the respective segment on a segment by segment basis.

摘要翻译： PCT No.PCT / US97 / 22102 Sec。 371日期1998年3月30日 102（e）1998年3月30日PCT 1997年12月5日PCT公布。 出版物WO99 /​​ 30326 日期1999年6月17日在扇区或芯片级擦除操作期间由驱动器使用的负电源电压与紧凑型字线驱动器和解码器系统中的单个字线驱动器的输入的解码分开解码。 一种集成电路存储器，包括布置在多个段中的存储器单元的阵列，一组字线耦合到阵列中的存储器单元，并且提供耦合到该组字线的字线驱动器电路。 字线驱动器电路包括第一电源电压源，第二电源电压源和一组字线驱动器。 字线驱动器耦合到第一和第二电源电压源，并且响应于识别相应驱动器的地址信号，用来自第一电源电压源或第二电源电压源的字线电压选择性地驱动字线组中的字线 。 第二电源电压源包括一组电源电压选择器。 该组中的每个电源电压选择器与该组驱动器的子集耦合。 驱动器的子集与阵列中的相应段耦合。 电源电压选择器响应于识别相应段的地址信号，在擦除模式期间选择负擦除电源电压或擦除禁止电源电压。 所选择的否定擦除电源电压或擦除禁止电源电压被施加到该组驱动器的子集，该组被分段地连接到相应的段。