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    Parallel push algorithm detecting constraints to minimize clock skew
    1.
    发明授权
    Parallel push algorithm detecting constraints to minimize clock skew 失效

    公开(公告)号：US06566924B2

    公开(公告)日：2003-05-20

    申请号：US09911398

    申请日：2001-07-25

    申请人： Shen Lin ,  Norman Chang ,  Keunmyung Lee ,  Osamu Nakagawa ,  Weize Xie

    发明人： Shen Lin ,  Norman Chang ,  Keunmyung Lee ,  Osamu Nakagawa ,  Weize Xie

    IPC分类号： H03L700

    CPC分类号： H03L7/00 ,  G06F1/10

    摘要： A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.

    Block-mode equalization for data communications
    2.
    发明授权
    Block-mode equalization for data communications 失效
    数据通信的块模式均衡

    公开(公告)号：US06584149B1

    公开(公告)日：2003-06-24

    申请号：US09415272

    申请日：1999-10-07

    申请人： Keunmyung Lee

    发明人： Keunmyung Lee

    IPC分类号： H03H730

    CPC分类号： H04L25/03885

    摘要： A signal equalization system provides a block-mode equalization system for digital equalization in computer and networking systems in which a “1” bit pulse is followed by a significant negative bit and less significant negative bit pulses as a multiple groups with a lower bit rate. The magnitude of the grouped bit pulses, or blocks of equalization bit pulses, can be the average value of the individual bits to produce a clean output waveform. Since the block compensates for the lower frequency response of the channel, its effectiveness is not sensitive to the exact location of the pulses. This makes it possible to align the blocks in wide pulses having decreasing magnitudes and increasing durations. This further means that when data multiplexing is involved in driver circuitry for the signal transmitter, the block can be generated from a lower frequency clocked domain before the multiplexing without burdening the high frequency side of the driver circuitry.

    摘要翻译： 信号均衡系统为计算机和网络系统中的数字均衡提供了块模式均衡系统，其中“1”位脉冲之后是显着的负位，而较小的负位脉冲作为具有较低位速率的多个组。 分组位脉冲或均衡位脉冲块的大小可以是产生干净输出波形的各个位的平均值。 由于该块补偿信道的较低频率响应，其有效性对于脉冲的确切位置不敏感。 这使得可以以具有降低的幅度和增加的持续时间的宽脉冲对准块。 这进一步意味着当信号发射器的驱动器电路涉及数据多路复用时，可以在多路复用之前从较低频率时钟域生成该块，而不会对驱动器电路的高频侧负担。

    USING STANDARD CURRENT CURVES TO CORRECT NON-UNIFORMITY IN ACTIVE MATRIX EMISSIVE DISPLAYS
    3.
    发明申请
    USING STANDARD CURRENT CURVES TO CORRECT NON-UNIFORMITY IN ACTIVE MATRIX EMISSIVE DISPLAYS 审中-公开
    使用标准电流曲线校正主动矩阵显示中的非均匀性

    公开(公告)号：US20090195483A1

    公开(公告)日：2009-08-06

    申请号：US12027000

    申请日：2008-02-06

    申请人： Walter Edward Naugler, JR. ,  Keunmyung Lee ,  Jose Ignacio Arreola

    发明人： Walter Edward Naugler, JR. ,  Keunmyung Lee ,  Jose Ignacio Arreola

    IPC分类号： G09G3/30

    CPC分类号： G09G3/3233 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/0276 ,  G09G2320/0285 ,  G09G2320/0295 ,  G09G2320/043 ,  G09G2320/0693

    摘要： A plurality of gray level versus OLED current curves are generated by measuring many OLED panels from a stable manufacturing process, and those curves are stored as standard gray level versus OLED current curves. When a new OLED display is manufactured from the process, each of its sub-pixels is characterized as having the characteristics of one of the pre-generated standard gray level versus OLED current curves, based on a gray level versus OLED current measurement at a single gray level. This drastically reduces the time it takes to determine the TFT gate voltage versus OLED current characteristics of the sub-pixels in the OLED display. The OLED display can use the selected one of the pre-generated standard gray level versus OLED current curves to correct non-uniformities of the sub-pixels in the OLED display caused by non-uniform TFTs in the active matrix.

    摘要翻译： 通过从稳定的制造过程测量许多OLED面板产生多个灰度级与OLED电流曲线，并且那些曲线被存储为与OLED电流曲线相关的标准灰度级。 当从该工艺制造新的OLED显示器时，其每个子像素的特征在于具有基于灰度级与OLED电流曲线之间的预先产生的标准灰度级与OLED电流曲线之一的特性 灰度级。 这大大减少了确定TFT显示器中的子像素的TFT栅极电压与OLED电流特性所需的时间。 OLED显示器可以使用所选择的预先生成的标准灰度级与OLED电流曲线来校正由有源矩阵中的不均匀TFT引起的OLED显示器中的子像素的不均匀性。

    Method and apparatus for driving STN LCD
    5.
    发明授权
    Method and apparatus for driving STN LCD 失效
    用于驱动STN LCD的方法和装置

    公开(公告)号：US06919872B2

    公开(公告)日：2005-07-19

    申请号：US10082942

    申请日：2002-02-25

    申请人： Tae-Kwang Park ,  Keunmyung Lee

    发明人： Tae-Kwang Park ,  Keunmyung Lee

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3625 ,  G09G2310/0208

    摘要： A driver for driving an STN LCD is disclosed. A preferred embodiment comprises a 3-line output display data for storing display data, an XOR block for finding mismatches between each 3-line output set of the stored display and orthogonal function signals, a decoder block for calculating mismatch numbers, a level shifter block for shifting the data level of the mismatch numbers to another level, and a voltage selector block for selecting a voltage level from 2 levels of voltage. Because data latches and output latches are not necessary, the driver of the present invention achieves significant reduction in the circuit components and chip size without compromising the display quality.

    摘要翻译： 公开了用于驱动STN LCD的驱动器。 优选实施例包括用于存储显示数据的3行输出显示数据，用于发现所存储的显示的每个3行输出组与正交函数信号之间的不匹配的异或块，用于计算不匹配数的解码器块，电平移位器块 用于将不匹配数据的数据电平移动到另一个电平;以及电压选择器块，用于从2个电压电平中选择电压电平。 因为不需要数据锁存器和输出锁存器，所以本发明的驱动器在不影响显示质量的情况下实现了电路部件和芯片尺寸的显着降低。

    Minimal length computer backplane
    6.
    发明授权
    Minimal length computer backplane 失效
    最小长度的计算机背板

    公开(公告)号：US5966293A

    公开(公告)日：1999-10-12

    申请号：US990635

    申请日：1997-12-15

    申请人： Hannsjorg Obermaier ,  Keunmyung Lee

    发明人： Hannsjorg Obermaier ,  Keunmyung Lee

    IPC分类号： G06F13/40 ,  H05K3/00 ,  H05K3/46 ,  H05K7/14 ,  H05K7/10

    CPC分类号： H05K3/4691 ,  G06F13/409 ,  H05K7/1442 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09109 ,  H05K3/4614

    摘要： An electrical interconnection structure. The electrical interconnection structure includes a mother board substrate having a plurality of layers. At least one layer includes a signal path having a characteristic impedance of Z.sub.O and a conductive ground plane. A signal via passes through each layer of the mother board substrate. The signal via electrically is connected to the signal path. A ground via passes through each layer of the mother board substrate. The ground via is electrically connected to the conductive ground plane. The electrical interconnection structure further includes a plurality of flex circuits. Each flex circuit includes a flex signal path having a characteristic impedance of Z.sub.O and a flex ground plane. Each flex signal path is electrically connected to the signal via and each flex ground plane is electrically connected to the ground via. The connections between the flex signal path and the signal via, and between the flex ground plane and the ground via can be permanent or separable.

    摘要翻译： 电互连结构。 电互连结构包括具有多个层的母板衬底。 至少一层包括具有ZO的特性阻抗和导电接地平面的信号路径。 信号通孔穿过母板基板的每一层。 电信号通过信号通路连接。 接地通孔穿过母板基板的每一层。 接地通孔电连接到导电接地平面。 电互连结构还包括多个柔性电路。 每个柔性电路包括具有ZO的特性阻抗和柔性接地平面的弯曲信号路径。 每个柔性信号路径电连接到信号通孔，并且每个柔性接地平面电连接到接地通孔。 柔性信号路径和信号通孔之间，以及柔性接地平面和接地通道之间的连接可以是永久的或可分离的。

    Single-scan driver for OLED display
    7.
    发明授权
    Single-scan driver for OLED display 失效
    用于OLED显示屏的单扫描驱动器

    公开(公告)号：US07046222B2

    公开(公告)日：2006-05-16

    申请号：US10232575

    申请日：2002-08-30

    申请人： Chang Oon Kim ,  Keunmyung Lee

    发明人： Chang Oon Kim ,  Keunmyung Lee

    IPC分类号： G09G3/32

    CPC分类号： G09G3/3216 ,  G09G3/3275 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0221 ,  G09G2320/0223 ,  G09G2320/043

    摘要： A single scan driver for an organic light emitting diode (OLED) display is disclosed, that can reduce the required power consumption. By connecting together both ends of each column line so that a single driver circuit can drive both ends of each column line together, the column line resistance is reduced, resulting in a significant reduction in power consumption.

    摘要翻译： 公开了用于有机发光二极管（OLED）显示器的单个扫描驱动器，其可以减少所需的功率消耗。 通过将每个列线的两端连接在一起，使得单个驱动器电路可以将每列列线的两端驱动在一起，减小列线电阻，导致功耗的显着降低。

    Computer-aided design methods and apparatus for multilevel interconnect technologies
    8.
    发明授权
    Computer-aided design methods and apparatus for multilevel interconnect technologies 失效
    用于多层互连技术的计算机辅助设计方法和装置

    公开(公告)号：US5610833A

    公开(公告)日：1997-03-11

    申请号：US533408

    申请日：1995-09-25

    申请人： Norman H. Chang ,  Keh-Jeng Chang ,  Keunmyung Lee ,  Soo-Young Oh

    发明人： Norman H. Chang ,  Keh-Jeng Chang ,  Keunmyung Lee ,  Soo-Young Oh

    IPC分类号： G06F17/50 ,  H01L23/528

    CPC分类号： G06F17/5077 ,  G06F17/5036 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： Data processing methods and computer display systems for computer aided design and electrical performance prediction of multilevel on-chip and off-chip interconnects. The invention specifically relates to parameterized graphical display and computation tools for calculation and display of capacitance and other electrical characteristics of multilevel VLSI, PCB, and MCM interconnects. Four subsystems are integrated: (a) a batch-mode computation module that combines a 2-D/3-D finite difference numerical simulation and a fast interpolation algorithm; (b) an interactive design mode with performance browsing, goal-directed synthesis, and on-line performance evaluation; (c) an interactive SPICE subcircuit generator and simulator; and (d) a spreadsheet-style graphical user interface.

    摘要翻译： 数据处理方法和计算机显示系统，用于多层片上和片外互连的计算机辅助设计和电气性能预测。 本发明具体涉及用于计算和显示多电平VLSI，PCB和MCM互连的电容和其他电特性的参数化图形显示和计算工具。 集成了四个子系统：（a）组合2-D / 3-D有限差分数值模拟和快速插值算法的批模式计算模块; （b）具有性能浏览，目标导向综合和在线性能评估的交互式设计模式; （c）交互式SPICE子电路发生器和仿真器; 和（d）电子表格式的图形用户界面。

    Via connection with thin resistivity layer
    10.
    发明授权
    Via connection with thin resistivity layer 失效
    通过连接薄电阻率层

    公开(公告)号：US4812419A

    公开(公告)日：1989-03-14

    申请号：US45002

    申请日：1987-04-30

    申请人： Keunmyung Lee ,  Yoshio Nishi

    发明人： Keunmyung Lee ,  Yoshio Nishi

    IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L11/00

    CPC分类号： H01L23/5226 ,  H01L2924/0002

    摘要： A via connection and method for making the same for integrated circuits having multiple layers of electrically conductive interconnect lines separated by an insulative layer. The via connection is characterized by a very thin layer of high resistivity material lining the via hole in conductive contact with interconnect lines in two layers. The resistivity of the thin layer material is in a range from about 10 to about 50 times the interconnect line resistivities and generally has a thickness of less than 100 nanometers. The thin layer assures more uniform current flow in the via connection thereby preventing electromigration, with reduced peak local current density by causing current to swing more widely around the corner at the interface between the interconnect lines at the via.