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    Frequency generation using a single reference clock and a primitive ratio of integers
    31.
    发明授权
    Frequency generation using a single reference clock and a primitive ratio of integers 有权
    使用单个参考时钟和原始整数比的频率生成

    公开(公告)号：US08554815B1

    公开(公告)日：2013-10-08

    申请号：US12621361

    申请日：2009-11-18

    申请人： Viet Linh Do ,  Simon Pang

    发明人： Viet Linh Do ,  Simon Pang

    IPC分类号： G06F1/02 ,  G06F7/52

    CPC分类号： E02F3/3609 ,  E02F3/3604 ,  E02F9/006

    摘要： A system and method are provided for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers. The method accepts a plurality (k) of reference frequency values (fri), where 1≦i≦k, associated with a corresponding plurality of synthesized frequency values (foi). For each synthesized frequency value, a raw ratio of integers Nprawi and Dprawi is calculated, such that: f o i = Np raw i Dp raw i × f r i . A greatest common divisor (GCD) of Nprawi and Dprawi and a primitive ratio of integers Np i Dp i is found for each raw ratio of integers, such that: N p i = Np raw i GCD ⁡ ( Np raw i , Dp raw i ) ; and , ⁢ D p i = Dp raw i GCD ⁡ ( Np raw i , Dp raw i ) . Using the common clock frequency value (fcr), each primitive ratio of integers, each reference frequency value, and each GCD, a final ratio of integers Ncri and Dcri, C · ( N cr i D cr i ) , is calculated for each synthesized frequency value, where C is an integer value.

    摘要翻译： 提供了一种用于使用单个参考时钟和整数的原始比来合成信号频率的系统和方法。 该方法接受与对应的多个合成频率值（foi）相关联的多个（k）个参考频率值（fri），其中1 @ i @ k。 对于每个合成频率值，计算整数Nprawi和Dprawi的原始比，使得：f o i = Np raw i Dp raw i×f r i。 对于每个原始的整数比，发现Nprawi和Dprawi的最大公约数（GCD）和整数Np i Dp i的原始比率，使得：N pi = Np raw i GCD⁡（Np raw i，Dp raw i） ; 和D p i = Dp raw i GCD⁡（Np raw i，Dp raw i）。 使用公共时钟频率值（fcr），对于每个合成的时钟频率值（fcr），计算每个原始比例的整数，每个参考频率值和每个GCD，整数Ncri和Dcri，C·（N cr i D cr i）的最终比率 频率值，其中C是整数值。

    Adaptive phase-locked loop (PLL) multi-band calibration
    32.
    发明授权
    Adaptive phase-locked loop (PLL) multi-band calibration 有权
    自适应锁相环（PLL）多频带校准

    公开(公告)号：US08358159B1

    公开(公告)日：2013-01-22

    申请号：US13045032

    申请日：2011-03-10

    申请人： Mehmet Mustafa Eker ,  Viet Do ,  Simon Pang

    发明人： Mehmet Mustafa Eker ,  Viet Do ,  Simon Pang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/095

    摘要： Adaptive multi-band frequency calibration is provided for a phase-locked loop (PLL). A voltage controller oscillator (VCO) is initially selected nominally associated with first synthesized signal frequency, where the VCO is selected from a plurality of n VCOs, and each VCO is tunable across a band of synthesized signal frequencies. A lock detector compares a nominal first synthesized signal frequency to a reference signal frequency. In response to sensing a difference between the nominal first synthesizer and reference signal frequencies, an out-of-lock condition is asserted and a VCO is reselected from the plurality of n VCOs. A mid-point control voltage is supplied to a control voltage input of the reselected VCO. A difference is measured between a mid-point synthesized signal frequency and the reference signal frequency. If the difference is less than a first threshold, the reselected VCO is assigned to generate the first synthesized signal frequency.

    摘要翻译： 为锁相环（PLL）提供自适应多频带频率校准。 最初选择与第一合成信号频率相关联的电压控制器振荡器（VCO），其中从多个n个VCO选择VCO，并且每个VCO可跨越合成信号频率的频带进行可调。 锁定检测器将标称第一合成信号频率与参考信号频率进行比较。 响应于感测标称第一合成器和参考信号频率之间的差异，断言失锁状态并且从多个n个VCO重新选择VCO。 中点控制电压被提供给重新选择的VCO的控制电压输入。 在中点合成信号频率和参考信号频率之间测量差异。 如果差值小于第一阈值，则重新选择的VCO被分配以产生第一合成信号频率。

    Automatic clock frequency acquisition
    33.
    发明授权
    Automatic clock frequency acquisition 有权
    自动时钟频率采集

    公开(公告)号：US08059778B1

    公开(公告)日：2011-11-15

    申请号：US12755292

    申请日：2010-04-06

    申请人： Viet Linh Do ,  Mehmet Mustafa Eker ,  Simon Pang

    发明人： Viet Linh Do ,  Mehmet Mustafa Eker ,  Simon Pang

    IPC分类号： H03D3/24

    CPC分类号： H03L7/113 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/1974 ,  H04L7/033 ,  H04L7/0331

    摘要： A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer ≧1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1=Fref1/(x−1).

    摘要翻译： 提供了一种用于自动获取串行数据流时钟的系统和方法。 该方法接收到具有未知时钟频率的串行数据流，并粗略地确定时钟频率。 通过（最初）选择高频第一参考时钟（Fref1）粗略地确定频率，并且以等于Fref1 / n的多个采样频率对串行数据流的第一时间段中的数据转换次数进行计数，其中 n为整数≧1。 将每个采样频率的计数与Fref1（n = 1）的计数进行比较。 接下来，确定最高采样频率（n = x），其具有比Fref1更低的计数，并且将粗略时钟频率设置为Fc1 = Fref1 /（x-1）。

    Frequency pattern detector
    34.
    发明授权
    Frequency pattern detector 有权
    频率模式检测器

    公开(公告)号：US07956649B1

    公开(公告)日：2011-06-07

    申请号：US12843534

    申请日：2010-07-26

    申请人： Simon Pang ,  Viet Do

    发明人： Simon Pang ,  Viet Do

    IPC分类号： H03D13/00

    CPC分类号： H03D13/00

    摘要： A window sampling system and method are provided for comparing a signal with an unknown frequency to a reference clock. A pattern modulator accepts a compClk signal and supplies a test window with a period equal to n compClk periods, where n is an integer greater than 1. A pattern detector accepts the test window and a reference clock, and contrasts the test window with the reference clock. In response to failing to fit n reference clock periods inside the test window, the pattern detector supplies a frequency pattern detector output signal (fpdOut) indicating that the frequency of the compClk is greater than the reference clock frequency.

    摘要翻译： 提供了一种用于将具有未知频率的信号与参考时钟进行比较的窗口采样系统和方法。 模式调制器接受compClk信号并提供具有等于n个compClk周期的周期的测试窗口，其中n是大于1的整数。模式检测器接受测试窗口和参考时钟，并将测试窗口与参考对象 时钟。 响应于在测试窗口内未配合n个参考时钟周期，模式检测器提供指示compClk的频率大于参考时钟频率的频率模式检测器输出信号（fpdOut）。

    High speed multi-modulus prescalar divider
    35.
    发明授权
    High speed multi-modulus prescalar divider 有权
    高速多模式预分频器

    公开(公告)号：US07826563B2

    公开(公告)日：2010-11-02

    申请号：US11717262

    申请日：2007-03-13

    申请人： Hongming An ,  Simon Pang ,  Viet Linh Do

    发明人： Hongming An ,  Simon Pang ,  Viet Linh Do

    IPC分类号： H03D3/24

    CPC分类号： H03L7/193 ,  G06F7/68 ,  H03K23/68

    摘要： A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.

    摘要翻译： 提供了一种用于多模式分割的系统和方法。 该方法接受具有第一频率的输入第一信号，并将第一频率除以整数。 利用具有第二频率的多个相位输出产生第二信号。 使用菊花链寄存器控制器，相位输出被选择并作为具有频率的第三个信号提供。 使用菊花链寄存器控制器选择相位输出包括将第三个信号作为时钟信号提供给具有以菊花链连接的输出的寄存器。 然后，响应于时钟信号产生寄存器输出脉冲序列，并且从序列中选择寄存器输出脉冲以选择第二信号相位输出。 通过使用8秒信号相位输出，获得第三个信号，频率等于第二个频率乘以以下数字之一：0.75,0.875,1,1125或1.25。

    System and method for automatic clock frequency acquisition
    36.
    发明授权
    System and method for automatic clock frequency acquisition 有权
    自动时钟频率采集的系统和方法

    公开(公告)号：US07720189B2

    公开(公告)日：2010-05-18

    申请号：US11595012

    申请日：2006-11-09

    申请人： Viet Linh Do ,  Mehmet Mustafa Eker ,  Simon Pang

    发明人： Viet Linh Do ,  Mehmet Mustafa Eker ,  Simon Pang

    IPC分类号： H03D3/24

    CPC分类号： H03L7/113 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/1974 ,  H04L7/033 ,  H04L7/0331

    摘要： A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer≧1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1 =Fref1/(x−1).

    摘要翻译： 提供了一种用于自动获取串行数据流时钟的系统和方法。 该方法接收到具有未知时钟频率的串行数据流，并粗略地确定时钟频率。 通过（最初）选择高频第一参考时钟（Fref1）粗略地确定频率，并且以等于Fref1 / n的多个采样频率对串行数据流的第一时间段中的数据转换次数进行计数，其中 n为整数≧1。 将每个采样频率的计数与Fref1（n = 1）的计数进行比较。 接下来，确定最高采样频率（n = x），其具有比Fref1更低的计数，并且将粗略时钟频率设置为Fc1 = Fref1 /（x-1）。

    High speed multi-modulus prescalar divider
    38.
    发明申请
    High speed multi-modulus prescalar divider 有权
    高速多模式预分频器

    公开(公告)号：US20080225989A1

    公开(公告)日：2008-09-18

    申请号：US11717262

    申请日：2007-03-13

    申请人： Hongming An ,  Simon Pang ,  Viet Linh Do

    发明人： Hongming An ,  Simon Pang ,  Viet Linh Do

    IPC分类号： H04L27/00

    CPC分类号： H03L7/193 ,  G06F7/68 ,  H03K23/68

    摘要： A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.

    摘要翻译： 提供了一种用于多模式分割的系统和方法。 该方法接受具有第一频率的输入第一信号，并将第一频率除以整数。 利用具有第二频率的多个相位输出产生第二信号。 使用菊花链寄存器控制器，相位输出被选择并作为具有频率的第三个信号提供。 使用菊花链寄存器控制器选择相位输出包括将第三个信号作为时钟信号提供给具有以菊花链连接的输出的寄存器。 然后，响应于时钟信号产生寄存器输出脉冲序列，并且从序列中选择寄存器输出脉冲以选择第二信号相位输出。 通过使用8秒信号相位输出，获得第三个信号，频率等于第二个频率乘以以下数字之一：0.75,0.875,1,1125或1.25。

    Frequency Synthesis Rational Division
    39.
    发明申请
    Frequency Synthesis Rational Division 有权
    频率综合理科

    公开(公告)号：US20080224735A1

    公开(公告)日：2008-09-18

    申请号：US12120027

    申请日：2008-05-13

    申请人： Viet Linh Do ,  Simon Pang ,  Hongming An ,  Jim Lew

    发明人： Viet Linh Do ,  Simon Pang ,  Hongming An ,  Jim Lew

    IPC分类号： H03B21/00

    CPC分类号： H03L7/1976 ,  G06F7/68 ,  H03K23/486

    摘要： A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q

    摘要翻译： 提供了一种使用合理划分来合成信号频率的系统和方法。 该方法接受参考频率值和合成频率值。 响应于将合成频率值除以参考频率值，确定整数值分子（dp）和整数值分母（dq）。 该方法降低了dp / dq与整数N的比值和p / q（dp / dq = N（p / q））的比值，其中p / q <1（十进制）。 分子（p）和分母（q）被提供给灵活的累加器模块，因此产生除数。 N与k位商相加以创建除数。 在锁相环（PLL）中，除数和参考信号用于产生频率等于合成频率值的合成信号。