公开(公告)号：US20140104960A1

公开(公告)日：2014-04-17

申请号：US13651698

申请日：2012-10-15

申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

IPC分类号： G11C7/12 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/1042 ,  G11C8/16 ,  G11C11/419

摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store digital data bits. SRAM memory circuits are generally read by decoding an address, reading from an addressed memory cell using a set of bit lines, outputting data from the read memory cell, and precharging the bit lines for a subsequent memory cycle. To handle memory operations faster, a bit line multiplexing system is proposed. Two sets of bit lines are coupled to each memory cell and each set of bit lines are used for memory operations in alternating memory cycles. During a first memory cycle, a first set of bit lines accesses the memory array while precharging a second set of bit lines. Then during a second memory cycle following the first memory cycle, the first set of bit lines are precharged while the second set of bit lines accesses the memory array to read data.

摘要翻译： 在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数字数据位。 通常通过对地址进行解码来读取SRAM存储器电路，使用一组位线从寻址的存储器单元读取，从读取的存储器单元输出数据，并为后续存储器周期预充电位线。 为了更快地处理存储器操作，提出了一种位线复用系统。 两组位线耦合到每个存储器单元，并且每组位线用于交替存储器周期中的存储器操作。 在第一存储器周期期间，第一组位线在对第二组位线进行预充电的同时访问存储器阵列。 然后在第一存储器周期之后的第二存储器周期期间，第一组位线被预充电，而第二组位线访问存储器阵列以读取数据。

公开(公告)号：US20130080694A1

公开(公告)日：2013-03-28

申请号：US13245426

申请日：2011-09-26

申请人： Sundar IYER ,  Shang-Tse CHUANG

发明人： Sundar IYER ,  Shang-Tse CHUANG

IPC分类号： G06F12/06

CPC分类号： G11C11/40603 ,  G11C11/40618

摘要： Dynamic memory systems require each memory cell to be continually refreshed. During a memory refresh operation, the refreshed memory cells cannot be accessed by a memory read or write operation. In multi-bank dynamic memory systems, concurrent refresh systems allow memory refresh circuitry to refresh memory banks that are not currently involved in memory access operations. To efficiently refresh memory banks and advanced round robin refresh system refreshes memory banks in a nominal round robin manner but skips memory banks blocked by memory access operations. Skipped memory banks are prioritized and then refreshed when they are no longer blocked.

摘要翻译： 动态存储器系统要求每个存储单元被不断刷新。 在存储器刷新操作期间，刷新的存储器单元不能被存储器读或写操作访问。 在多行动态存储器系统中，并发刷新系统允许存储器刷新电路来刷新当前不参与存储器存取操作的存储器组。 为了有效地刷新内存库和高级循环刷新系统，以一种名义上的循环方式刷新内存库，但是忽略了内存访问操作阻塞的内存块。 跳过的内存库被优先排列，然后在不再被阻止时刷新。

公开(公告)号：US08266408B2

公开(公告)日：2012-09-11

申请号：US12653660

申请日：2009-12-15

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F13/00

CPC分类号： G06F12/1009 ,  G06F12/06 ,  G06F12/0851 ,  G06F12/10 ,  G11C7/1075

摘要： A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict.

摘要翻译： 公开了一种用于提供高速存储器操作的系统和方法。 该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。 更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。

公开(公告)号：US20110167192A1

公开(公告)日：2011-07-07

申请号：US12653660

申请日：2009-12-15

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F12/06 ,  G06F12/0851 ,  G06F12/10 ,  G11C7/1075

摘要： A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict.

摘要翻译： 公开了一种用于提供高速存储器操作的系统和方法。 该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。 更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。

公开(公告)号：US20100241784A1

公开(公告)日：2010-09-23

申请号：US12584645

申请日：2009-09-08

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0292 ,  G06F12/06 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/502 ,  G06F2212/657

摘要： A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict.

摘要翻译： 公开了一种用于提供高速存储器操作的系统和方法。 该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。 更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。

公开(公告)号：US20060031565A1

公开(公告)日：2006-02-09

申请号：US11182731

申请日：2005-07-15

申请人： Sundar Iyer ,  Nick McKeown ,  Jeff Chou

发明人： Sundar Iyer ,  Nick McKeown ,  Jeff Chou

IPC分类号： G06F15/16

CPC分类号： H04L49/901 ,  H04L49/90 ,  H04L49/9047 ,  H04L49/9057

摘要： A number of techniques for implementing packet-buffering memory systems and packet-buffering memory architectures are disclosed. In one embodiment, a packet-buffering memory system comprises a high-latency memory sub system with a latency time of L and a low-latency memory subsystem. The low-latency memory subsystem contains enough memory to store an amount of packet data to last L seconds when accessed from low-latency memory subsystem at an access-rate of A. The packet-buffering system further comprises a FIFO controller that responds to a packet read request by simultaneously requesting packet data from said high-latency memory subsystem while simultaneously requesting and quickly responding with packet data obtained from the low-latency memory subsystem.

摘要翻译： 公开了用于实现分组缓冲存储器系统和分组缓冲存储器架构的许多技术。 在一个实施例中，分组缓冲存储器系统包括具有等待时间L的高延迟存储器子系统和低延迟存储器子系统。 低延迟存储器子系统包含足够的存储器，用于存储从A的访问速率低的低延迟存储器子系统访问时持续L秒的分组数据量。分组缓冲系统还包括FIFO控制器，其响应于 通过从所述高延迟存储器子系统同时请求分组数据同时请求并且从低延迟存储器子系统获得的分组数据快速响应来分组读请求。

公开(公告)号：US20050240745A1

公开(公告)日：2005-10-27

申请号：US11016572

申请日：2004-12-17

申请人： Sundar Iyer ,  Nick McKeown

发明人： Sundar Iyer ,  Nick McKeown

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16

CPC分类号： G06F13/1668 ,  G06F12/0223 ,  G06F12/0607 ,  G06F2212/205

摘要： An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.

摘要翻译： 提出了一种用于加速处理器的输入/输出和存储器访问操作的输入/输出处理器。 输入/输出处理器的关键思想是将输入/输出和存储器访问操作任务功能划分为由处理器处理的计算密集型部分以及I / O或存储器密集部分，然后由输入/输出处理 处理器。 输入/输出处理器是通过分析常用的输入/输出和存储器访问模式来设计的，并且实现了有效处理这些常见模式的方法。 输入/输出处理器可以使用的一种技术是将存储器任务分为高频或高可用性组件以及低频或低可用性组件。 在以这种方式分配存储器任务之后，输入/输出处理器然后使用高速存储器（例如SRAM）来存储高频和高可用性组件以及较慢速存储器（例如商品DRAM）来存储 低频和低可用性组件。 输入/输出处理器使用的另一技术是以消除所有存储器组冲突的方式分配存储器。 通过消除任何可能的存储体冲突，可以实现DRAM存储器技术的最大随机存取性能。