公开(公告)号：US20060031565A1

公开(公告)日：2006-02-09

申请号：US11182731

申请日：2005-07-15

申请人： Sundar Iyer ,  Nick McKeown ,  Jeff Chou

发明人： Sundar Iyer ,  Nick McKeown ,  Jeff Chou

IPC分类号： G06F15/16

CPC分类号： H04L49/901 ,  H04L49/90 ,  H04L49/9047 ,  H04L49/9057

摘要： A number of techniques for implementing packet-buffering memory systems and packet-buffering memory architectures are disclosed. In one embodiment, a packet-buffering memory system comprises a high-latency memory sub system with a latency time of L and a low-latency memory subsystem. The low-latency memory subsystem contains enough memory to store an amount of packet data to last L seconds when accessed from low-latency memory subsystem at an access-rate of A. The packet-buffering system further comprises a FIFO controller that responds to a packet read request by simultaneously requesting packet data from said high-latency memory subsystem while simultaneously requesting and quickly responding with packet data obtained from the low-latency memory subsystem.

摘要翻译： 公开了用于实现分组缓冲存储器系统和分组缓冲存储器架构的许多技术。 在一个实施例中，分组缓冲存储器系统包括具有等待时间L的高延迟存储器子系统和低延迟存储器子系统。 低延迟存储器子系统包含足够的存储器，用于存储从A的访问速率低的低延迟存储器子系统访问时持续L秒的分组数据量。分组缓冲系统还包括FIFO控制器，其响应于 通过从所述高延迟存储器子系统同时请求分组数据同时请求并且从低延迟存储器子系统获得的分组数据快速响应来分组读请求。

公开(公告)号：US20060123139A1

公开(公告)日：2006-06-08

申请号：US11222387

申请日：2005-09-07

申请人： Sundar Iyer ,  Nick McKeown ,  Morgan Littlewood

发明人： Sundar Iyer ,  Nick McKeown ,  Morgan Littlewood

IPC分类号： G06F3/00

CPC分类号： G06F1/3209 ,  H04L49/3009 ,  H04L49/3036 ,  H04L49/90

摘要： The present invention introduces various high-level memory interfaces for interfacing with an intelligent memory system. The memory interfaces may be hardware-based or software-based. In one embodiment, two layers of interfaces are implemented such that an internal interface may evolve over successive generations without affecting an externally visible interface.

摘要翻译： 本发明引入了用于与智能存储器系统接口的各种高级存储器接口。 存储器接口可以是基于硬件的或基于软件的。 在一个实施例中，实现两层接口，使得内部接口可以在连续世代上演进而不影响外部可见接口。

公开(公告)号：USRE45097E1

公开(公告)日：2014-08-26

申请号：US13365136

申请日：2012-02-02

申请人： Sundar Iyer ,  Nick McKeown

发明人： Sundar Iyer ,  Nick McKeown

IPC分类号： G06F13/00

CPC分类号： G06F13/1668 ,  G06F12/0223 ,  G06F12/0607 ,  G06F2212/205

摘要： An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.

摘要翻译： 提出了一种用于加速处理器的输入/输出和存储器访问操作的输入/输出处理器。 输入/输出处理器的关键思想是将输入/输出和存储器访问操作任务功能划分为由处理器处理的计算密集型部分以及I / O或存储器密集部分，然后由输入/输出处理 处理器。 输入/输出处理器是通过分析常用的输入/输出和存储器访问模式来设计的，并且实现了有效处理这些常见模式的方法。 输入/输出处理器可以使用的一种技术是将存储器任务分为高频或高可用性组件以及低频或低可用性组件。 在以这种方式分配存储器任务之后，输入/输出处理器然后使用高速存储器（例如SRAM）来存储高频和高可用性组件以及较慢速存储器（例如商品DRAM）来存储 低频和低可用性组件。 输入/输出处理器使用的另一技术是以消除所有存储器组冲突的方式分配存储器。 通过消除任何可能的存储体冲突，可以实现DRAM存储器技术的最大随机存取性能。

公开(公告)号：US09274586B2

公开(公告)日：2016-03-01

申请号：US11222387

申请日：2005-09-07

申请人： Sundar Iyer ,  Nick McKeown ,  Morgan Littlewood

发明人： Sundar Iyer ,  Nick McKeown ,  Morgan Littlewood

IPC分类号： G06F12/00 ,  G06F1/32 ,  H04L12/861 ,  H04L12/935

CPC分类号： G06F1/3209 ,  H04L49/3009 ,  H04L49/3036 ,  H04L49/90

摘要： Many computer processing tasks require large numbers of memory intensive operations to be performed very rapidly. For example, computer network requires that packets be placed into and removed from First-In First-Out (FIFO) queues, numerous counters to be maintained and routing table look-ups to be performed. All of these operations must be performed at very high-speeds in order to keep up with today's high-speed computer network traffic. To help perform these high-speed memory tasks, a high-speed intelligent memory subsystem has been developed. The high-speed intelligent memory subsystem handles the intricacies of these memory operations such that a main process is relieved of some of its duties. Various different high-level memory interfaces for interfacing with the intelligent memory subsystem. The memory interfaces may be hardware-based or software-based. In one embodiment, two layers of interfaces are implemented such that an internal interface may evolve over successive generations without affecting an externally visible interface.

摘要翻译： 许多计算机处理任务需要非常快速地执行大量的内存密集型操作。 例如，计算机网络要求将数据包放入先入先出（FIFO）队列中的数据包，要保留的许多计数器和要执行的路由表查找。 所有这些操作必须以非常高的速度执行，以便跟上当今的高速计算机网络流量。 为了帮助执行这些高速存储器任务，开发了高速智能存储器子系统。 高速智能存储器子系统处理这些记忆操作的复杂性，使得主程序免除了其一些职责。 各种不同的高级存储器接口，用于与智能存储器子系统进行接口。 存储器接口可以是基于硬件的或基于软件的。 在一个实施例中，实现两层接口，使得内部接口可以在连续世代上演进而不影响外部可见接口。

公开(公告)号：US07657706B2

公开(公告)日：2010-02-02

申请号：US11016572

申请日：2004-12-17

申请人： Sundar Iyer ,  Nick McKeown

发明人： Sundar Iyer ,  Nick McKeown

IPC分类号： G06F13/00

CPC分类号： G06F13/1668 ,  G06F12/0223 ,  G06F12/0607 ,  G06F2212/205

摘要： An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.

摘要翻译： 提出了一种用于加速处理器的输入/输出和存储器访问操作的输入/输出处理器。 输入/输出处理器的关键思想是将输入/输出和存储器访问操作任务功能划分为由处理器处理的计算密集型部分以及I / O或存储器密集部分，然后由输入/输出处理 处理器。 输入/输出处理器是通过分析常用的输入/输出和存储器访问模式来设计的，并且实现了有效处理这些常见模式的方法。 输入/输出处理器可以使用的一种技术是将存储器任务分为高频或高可用性组件以及低频或低可用性组件。 在以这种方式分配存储器任务之后，输入/输出处理器然后使用高速存储器（例如SRAM）来存储高频和高可用性组件以及较慢速存储器（例如商品DRAM）来存储 低频和低可用性组件。 输入/输出处理器使用的另一技术是以消除所有存储器组冲突的方式分配存储器。 通过消除任何可能的存储体冲突，可以实现DRAM存储器技术的最大随机存取性能。

公开(公告)号：US20050240745A1

公开(公告)日：2005-10-27

申请号：US11016572

申请日：2004-12-17

申请人： Sundar Iyer ,  Nick McKeown

发明人： Sundar Iyer ,  Nick McKeown

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16

CPC分类号： G06F13/1668 ,  G06F12/0223 ,  G06F12/0607 ,  G06F2212/205

摘要： An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.

摘要翻译： 提出了一种用于加速处理器的输入/输出和存储器访问操作的输入/输出处理器。 输入/输出处理器的关键思想是将输入/输出和存储器访问操作任务功能划分为由处理器处理的计算密集型部分以及I / O或存储器密集部分，然后由输入/输出处理 处理器。 输入/输出处理器是通过分析常用的输入/输出和存储器访问模式来设计的，并且实现了有效处理这些常见模式的方法。 输入/输出处理器可以使用的一种技术是将存储器任务分为高频或高可用性组件以及低频或低可用性组件。 在以这种方式分配存储器任务之后，输入/输出处理器然后使用高速存储器（例如SRAM）来存储高频和高可用性组件以及较慢速存储器（例如商品DRAM）来存储 低频和低可用性组件。 输入/输出处理器使用的另一技术是以消除所有存储器组冲突的方式分配存储器。 通过消除任何可能的存储体冲突，可以实现DRAM存储器技术的最大随机存取性能。

公开(公告)号：US08589851B2

公开(公告)日：2013-11-19

申请号：US12806946

申请日：2010-08-23

申请人： Sundar Iyer ,  Sanjeev Joshi ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Sanjeev Joshi ,  Shang-Tse Chuang

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F3/0607 ,  G06F3/0629 ,  G06F3/0683 ,  G06F12/0844 ,  G06F12/0851 ,  G06F12/0855

摘要： Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.

摘要翻译： 为集成电路设计存储器子系统可能是耗时且昂贵的任务。 为了减少开发时间和成本，公开了一种用于设计和构建高速存储器操作的自动化系统和方法。 自动化系统接受一组期望的存储特性，然后有选择地选择不同的潜在存储器系统设计类型和每种存储器系统设计类型的不同实现。 潜在的存储器系统设计类型可以包括传统的存储器系统，优化的传统存储器系统，智能存储器系统和分层存储器系统。 满足所指定的所需存储器特性集合的一组选定的存储器系统被输出到电路设计者。 当电路设计者选择所提出的存储器系统时，自动化系统产生完整的存储器系统设计，存储器系统的模型以及存储器系统的测试套件。

公开(公告)号：US20130242677A1

公开(公告)日：2013-09-19

申请号：US13421704

申请日：2012-03-15

申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

IPC分类号： G11C8/16 ,  G11C7/00

CPC分类号： G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

摘要： To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

摘要翻译： 为了处理多个并发存储器请求，提出了一个双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问位单元的真实侧和假侧。 单端读取允许内存系统同时处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 位单元格。 因此，具有电压辅助的单端操作允许存储器系统处理两个并行写入操作。 可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

公开(公告)号：US08504796B2

公开(公告)日：2013-08-06

申请号：US13570125

申请日：2012-08-08

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F13/00

CPC分类号： G06F12/1009 ,  G06F12/06 ,  G06F12/0851 ,  G06F12/10 ,  G11C7/1075

摘要： A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. A changeable mapping table that maps the virtualized memory addresses to physical memory addresses is stored in the same memory system.

摘要翻译： 公开了一种用于提供高速存储器操作的系统和方法。 该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。 更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。 将虚拟内存地址映射到物理内存地址的可更改映射表存储在同一个内存系统中。

公开(公告)号：US20110145513A1

公开(公告)日：2011-06-16

申请号：US12928698

申请日：2010-12-15

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F12/08

CPC分类号： G06F12/0844 ,  G06F12/0851 ,  G06F12/0855 ,  G06F12/10

摘要： A reduced latency memory system that prevents memory bank conflicts. The reduced latency memory system receives a read request and write request. The read request is then handled by simultaneously fetching data from a main memory and a cache memory. The address of the read request is compared with a cache tag value and if the cache tag value matches the address of the read request, the data from the cache memory is served. The write request is stored and handled in a subsequent memory cycle.

摘要翻译： 减少延迟的存储器系统，防止存储器冲突。 减少延迟的存储器系统接收读请求和写请求。 然后通过从主存储器和高速缓冲存储器同时提取数据来处理读请求。 将读取请求的地址与缓存标签值进行比较，并且如果高速缓存标签值与读取请求的地址匹配，则来自高速缓冲存储器的数据被提供。 写请求在随后的存储器周期中被存储和处理。