公开(公告)号：US20080150013A1

公开(公告)日：2008-06-26

申请号：US11644344

申请日：2006-12-22

申请人： Sung-Shan Tai ,  Yong-Zhong Hu ,  Francois Hebert ,  Hong Chang ,  Mengyu Pan ,  Yingying Lou ,  Yu Wang

发明人： Sung-Shan Tai ,  Yong-Zhong Hu ,  Francois Hebert ,  Hong Chang ,  Mengyu Pan ,  Yingying Lou ,  Yu Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/66734

摘要： This invention discloses method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.

摘要翻译： 本发明公开了一种制造半导体功率器件的方法，该沟槽半导体功率器件具有填充在半导体衬底中开口的沟槽的分离栅极，其中，分离栅极由设置在顶部和底部栅极段之间的多晶硅绝缘层分开。 该方法还包括通过在HDP氧化物沉积工艺之后施加RTP工艺以形成HDP氧化物层的蚀刻速率接近热氧化物的蚀刻速率来形成多晶硅层之间的步骤。

公开(公告)号：US09337329B2

公开(公告)日：2016-05-10

申请号：US13199795

申请日：2011-09-08

申请人： Yongzhong Hu ,  Sung-Shan Tai

发明人： Yongzhong Hu ,  Sung-Shan Tai

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L29/7813 ,  H01L21/28518 ,  H01L21/823418 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/1082

摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may further be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

摘要翻译： 沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。 围绕沟槽栅极的源极区域包括低势垒高度的金属，用作肖特基源并且可以包括PtSi，ErSi层，并且还可以是具有低势垒高度的金属硅化物层。 顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。 源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。

公开(公告)号：US08835251B2

公开(公告)日：2014-09-16

申请号：US12928813

申请日：2010-12-20

申请人： YongZhong Hu ,  Sung-Shan Tai

发明人： YongZhong Hu ,  Sung-Shan Tai

IPC分类号： H01L27/06 ,  H01L49/02

CPC分类号： H01L27/0629 ,  H01L28/20 ,  H01L28/60 ,  Y10S438/957

摘要： A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.

摘要翻译： 半导体器件包括晶体管，电容器和电阻器，其中电容器包括用作底部导电层的掺杂多晶硅层，其中具有作为顶部导电的Ti / TiN层覆盖的电介质层的硅化物块（SAB）层 从而构成单个多晶硅层金属 - 绝缘体 - 多晶硅（MIP）结构。 虽然高片rho电阻也形成在同一个多晶硅层上，多晶硅层的差分掺杂。

公开(公告)号：US20140179074A1

公开(公告)日：2014-06-26

申请号：US13722930

申请日：2012-12-20

申请人： Ji Pan ,  Daniel Ng ,  Sung-Shan Tai ,  Anup Bhalla

发明人： Ji Pan ,  Daniel Ng ,  Sung-Shan Tai ,  Anup Bhalla

IPC分类号： H01L21/82

CPC分类号： H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/82 ,  H01L21/823412 ,  H01L27/0629 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/4916 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)

摘要翻译： 公开了一种用于制造与肖特基二极管（MOSFET / SKY）集成的MOSFET的方法。 栅极沟槽形成在覆盖半导体衬底的外延层中，栅极材料沉积在其中。 主体，源极，电介质区域依次形成在外延层和栅极沟槽上。 通过定义源极接触深度（SCD）的电介质和源极区域，用垂直侧壁蚀刻顶部接触沟槽（TCT），所述垂直侧壁限定肖特基二极管横截面宽度SDCW; 并通过全身接触深度（TBCD）部分进入体区。 身体接触深度（BCD）

公开(公告)号：US08748268B1

公开(公告)日：2014-06-10

申请号：US13722930

申请日：2012-12-20

申请人： Ji Pan ,  Daniel Ng ,  Sung-Shan Tai ,  Anup Bhalla

发明人： Ji Pan ,  Daniel Ng ,  Sung-Shan Tai ,  Anup Bhalla

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/82 ,  H01L21/823412 ,  H01L27/0629 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/4916 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)

摘要翻译： 公开了一种用于制造与肖特基二极管（MOSFET / SKY）集成的MOSFET的方法。 栅极沟槽形成在覆盖半导体衬底的外延层中，栅极材料沉积在其中。 主体，源极，电介质区域依次形成在外延层和栅极沟槽上。 通过定义源极接触深度（SCD）的电介质和源极区域，用垂直侧壁蚀刻顶部接触沟槽（TCT），所述垂直侧壁限定肖特基二极管横截面宽度SDCW; 并通过全身接触深度（TBCD）部分进入体区。 身体接触深度（BCD）

公开(公告)号：US08643094B2

公开(公告)日：2014-02-04

申请号：US13218476

申请日：2011-08-26

申请人： Sung-Shan Tai ,  Teng-hao Yeh ,  Chia-Hui Chen

发明人： Sung-Shan Tai ,  Teng-hao Yeh ,  Chia-Hui Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.

摘要翻译： 提出了在半导体衬底中形成接触开口的方法。 在半导体衬底中形成各自具有突出部分的多个沟槽栅极，并且在突出部分上延伸的半导体衬底上沉积停止层，其中沿着突出部分的每个侧壁的阻挡层的每个部分是 被间隔物覆盖。 通过利用阻挡层对间隔物的相对较高的蚀刻选择性去除未被间隔物覆盖的停止层的部分，可以形成每个侧壁上具有L型形状的相邻突出部分之间的开口，并且可以形成光刻 此后可以进行处理以形成自对准的接触开口。

公开(公告)号：US08394702B2

公开(公告)日：2013-03-12

申请号：US12782573

申请日：2010-05-18

申请人： Sung-Shan Tai ,  Sik Lui ,  Xiaobin Wang

发明人： Sung-Shan Tai ,  Sik Lui ,  Xiaobin Wang

IPC分类号： H01L21/336 ,  H01L21/8249 ,  H01L21/425 ,  H01L21/20 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

摘要翻译： 公开了半导体器件和制造方法。 该器件包括形成在位于半导体衬底的有源区中的沟槽中的多个栅电极。 第一栅极流道形成在基板中并电连接到栅电极，其中第一栅极流道围绕有源区。 第二浇口浇道连接到第一浇口浇道并且位于活性区域和终止区域之间。 终端结构围绕第一和第二栅极流道和有源区域。 端接结构包括在衬底中的绝缘体衬里的沟槽中的导电材料，其中端接结构电气短路到衬底的源极或体层，从而形成用于器件的通道停止。

公开(公告)号：US08193061B2

公开(公告)日：2012-06-05

申请号：US13066583

申请日：2011-04-18

申请人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

发明人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L22/12 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

摘要翻译： 本发明公开了一种用于在其上制造电子电路的半导体晶片。 半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部 具有较小的平面沟槽尺寸。

公开(公告)号：US08187939B2

公开(公告)日：2012-05-29

申请号：US12565611

申请日：2009-09-23

申请人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

发明人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 可以将沟槽掩模施加到半导体衬底，其被蚀刻以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上形成第二导电材料。 绝缘体层分离第一和第二导电材料。 第一绝缘体层沉积在沟槽的顶部。 主体层形成在基板的顶部。 源体形成在体层中。 第二绝缘体层被施加在沟槽和源的顶部上。 接触掩模施加在第二绝缘体层的顶部。 源极和栅极触点通过第二绝缘体层形成。 源极和栅极金属形成在第二绝缘体层的顶部上。

公开(公告)号：US20120018793A1

公开(公告)日：2012-01-26

申请号：US13200869

申请日：2011-10-04

申请人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K. Lui

发明人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K. Lui

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

摘要翻译： 本发明公开了一种半导体功率器件。 沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。 所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域 从而可以减少用于制造半导体功率器件的掩模。