公开(公告)号：US10818356B2

公开(公告)日：2020-10-27

申请号：US16263604

申请日：2019-01-31

申请人： UNITED SEMICONDUCTOR JAPAN CO., LTD

发明人： Satoshi Torii ,  Shu Ishihara

IPC分类号： G11C16/04 ,  H01L27/11529 ,  H01L27/11524 ,  G11C16/26

摘要： A nonvolatile semiconductor memory device includes a selection transistor and a memory transistor that are formed on a well for each of a plurality of memory cells. At a time of a data read from the memory transistor, a first voltage is applied to the well and a source of the memory transistor, and a second voltage is applied to a gate of the selection transistor included in a non-selected memory cell among the plurality of memory cells. The first voltage is smaller than an absolute value of the second voltage.

公开(公告)号：US20200287009A1

公开(公告)日：2020-09-10

申请号：US16807614

申请日：2020-03-03

申请人： United Semiconductor Japan Co. Ltd.

发明人： Toru Anezaki ,  Fumitaka Ohno

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092

摘要： A semiconductor device includes a semiconductor substrate, a gate electrode disposed over the semiconductor substrate and extending in a first direction, a dummy gate electrode disposed over the semiconductor substrate away from the gate electrode and extending in the first direction, a first semiconductor area of a first conductive type disposed in a surface layer portion of the semiconductor substrate between the gate electrode and the dummy gate electrode, and a conductor electrically connecting the first semiconductor area with the dummy gate electrode.

公开(公告)号：US10720489B2

公开(公告)日：2020-07-21

申请号：US16460400

申请日：2019-07-02

申请人： UNITED SEMICONDUCTOR JAPAN CO., LTD.

发明人： Taiji Ema ,  Nobuhiro Misawa ,  Kazuyuki Kumeno ,  Makoto Yasuda

IPC分类号： H01L27/06 ,  H01L49/02 ,  H01L27/08

摘要： A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.

公开(公告)号：US20200152626A1

公开(公告)日：2020-05-14

申请号：US16745896

申请日：2020-01-17

申请人： United Semiconductor Japan Co., Ltd.

发明人： David A. Kidd

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H03K3/356 ,  H03K5/05 ,  H03L7/081 ,  G11C7/06 ,  H01L29/10 ,  G11C7/08 ,  H03L7/08 ,  H03K5/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/36 ,  H03K17/687

摘要： An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

公开(公告)号：US11255011B1

公开(公告)日：2022-02-22

申请号：US17024677

申请日：2020-09-17

申请人： United Semiconductor Japan Co., Ltd.

发明人： Satoshi Inagaki

IPC分类号： C23C14/04 ,  C23C16/04 ,  G03F7/20

摘要： A mask structure for a deposition device includes first segments and second segments. The first segments are arranged in a direction surrounding a central axis and separated from one another. The second segments are disposed above the first segments. Each of the second segments overlaps two of the first segments adjacent to each other in a vertical direction parallel to an extending direction of the central axis. A deposition device includes a process chamber, a stage, and the mask structure. The stage is at least partially disposed in the process chamber and includes a holding structure of a substrate. The mask structure is disposed in the process chamber, located over the stage, and covers a peripheral region of the substrate to be held on the stage. An operation method of the deposition device includes horizontally adjusting positions of the first segments and the second segments respectively between different deposition processes.