公开(公告)号：US07932542B2

公开(公告)日：2011-04-26

申请号：US11860413

申请日：2007-09-24

申请人： Joerg Berthold ,  Winfried Kamp ,  Fritz Rothacher

发明人： Joerg Berthold ,  Winfried Kamp ,  Fritz Rothacher

IPC分类号： H01L27/118

CPC分类号： H01L27/0207 ,  H01L21/823807 ,  H01L27/11803 ,  H01L29/7843

摘要： A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.

摘要翻译： 一种制造集成电路的方法，包括布置多个单元以形成集成电路的所需平面图，其中每个单元包括至少一个晶体管，从平面图的多个单元形成多个电路组件，其中 每个电路组件包括至少一个小区，属于多个电路组成类型中的一个，并且基于小区所属的电路组件的电路组成类型，对每个小区的至少一个晶体管的沟道区域施加机械应力 。

公开(公告)号：US20100308863A1

公开(公告)日：2010-12-09

申请号：US12780772

申请日：2010-05-14

申请人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

发明人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

IPC分类号： H03K19/177

CPC分类号： H03K19/1735 ,  H01L27/11807

摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

摘要翻译： 集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。 布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。 此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

公开(公告)号：US07755110B2

公开(公告)日：2010-07-13

申请号：US11088506

申请日：2005-03-24

申请人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

发明人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

IPC分类号： H01L27/10

CPC分类号： H03K19/1735 ,  H01L27/11807

摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

摘要翻译： 集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。 布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。 此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

公开(公告)号：US07716270B2

公开(公告)日：2010-05-11

申请号：US11374396

申请日：2006-03-13

申请人： Joel Hatsch ,  Winfried Kamp

发明人： Joel Hatsch ,  Winfried Kamp

IPC分类号： G06F7/50

CPC分类号： G06F7/503

摘要： A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry outputs for outputting three output carry bits having the significance 2w.

摘要翻译： 进位纹波加法器具有四个加法输入，用于接收具有要求和的有效值w的四个输入位，三个进位输入用于接收具有有效值w的三个输入进位位;一个求和输出，用于输出具有重要性的输出求和位 w和三个进位输出，用于输出具有重要性2w的三个输出进位。

公开(公告)号：US07439765B2

公开(公告)日：2008-10-21

申请号：US11437435

申请日：2006-05-19

申请人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

发明人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

IPC分类号： H03K19/173

CPC分类号： H03K19/17748 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/1778 ,  H01L2924/00

摘要： A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors formed on a semiconductor substrate, each of the transistors comprising a controllable path and a control terminal. The controllable paths can be connected in series with one another between a first supply terminal and the output terminal by metallizing first metallization regions. The the transistors of the first set of transistors are arranged on the semiconductor substrate in such a way that at least one controllable path of the transistors can be bridged by metallizing one of the first metallization regions. A respective of the input terminals can be connected to a respective of the control terminals by metallizing a second metallization region.

摘要翻译： 掩模可编程逻辑宏包括至少三个输入端子，输出端子和由形成在半导体衬底上的至少三个晶体管组成的第一组晶体管，每个晶体管包括可控路径和控制端子。 可控路径可以通过金属化第一金属化区域而在第一电源端子和输出端子之间彼此串联连接。 第一组晶体管的晶体管以这样的方式被布置在半导体衬底上，使得可以通过金属化第一金属化区域之一来桥接晶体管的至少一个可控路径。 可以通过金属化第二金属化区域来将各个输入端子连接到相应的控制端子。

公开(公告)号：US20080185688A1

公开(公告)日：2008-08-07

申请号：US11969888

申请日：2008-01-05

申请人： Andreas Kuesel ,  Julie Aunis ,  Winfried Kamp

发明人： Andreas Kuesel ,  Julie Aunis ,  Winfried Kamp

IPC分类号： H01L29/06 ,  G06F17/50

CPC分类号： G06F17/5072

摘要： Various methods for determining a layout of an integrated circuit are described. For example, a method is described comprising determining a layout of an integrated circuit comprising a plurality of functional cells, wherein a maximum extent of each of the cells in a first direction is identical and wherein an outer boundary of a first cell of the plurality of cells forms a first polygon with at least five corner points; and storing data representing the layout on a computer-readable medium. Integrated circuits in accordance with the layout are also described.

摘要翻译： 描述用于确定集成电路的布局的各种方法。 例如，描述了一种方法，其包括确定包括多个功能单元的集成电路的布局，其中第一方向上的每个单元的最大范围是相同的，并且其中多个单元的第一单元的外边界 细胞形成具有至少五个角点的第一多边形; 以及将表示所述布局的数据存储在计算机可读介质上。 还描述了根据布局的集成电路。

公开(公告)号：US06978290B2

公开(公告)日：2005-12-20

申请号：US10116851

申请日：2002-04-05

申请人： Joel Hatsch ,  Winfried Kamp ,  Siegmar Köppe ,  Ronald Künemund ,  Eva Lackerschmid ,  Heinz Söldner

发明人： Joel Hatsch ,  Winfried Kamp ,  Siegmar Köppe ,  Ronald Künemund ,  Eva Lackerschmid ,  Heinz Söldner

IPC分类号： G06F7/50 ,  G06F7/60

CPC分类号： G06F7/607

摘要： A carry ripple adder contains five first inputs for accepting five input bits having equal significance w that are to be summed and two second inputs for accepting two carry bits having the significance w. It also contains an output for a sum bit having the significance w and two outputs for two carry bits having the significances 2w and 4w.

摘要翻译： 进位纹波加法器包含五个第一输入，用于接受具有相等的有效w的五个输入比特，并且两个第二输入用于接受具有重要性w的两个进位。 它还包含一个具有重要性w的和位的输出和两个具有重要性2w和4w的进位位的两个输出。

公开(公告)号：US06977831B2

公开(公告)日：2005-12-20

申请号：US10943701

申请日：2004-09-17

申请人： Joel Hatsch ,  Winfried Kamp ,  Thomas Künemund ,  Holger Sedlak ,  Heinz Söldner

发明人： Joel Hatsch ,  Winfried Kamp ,  Thomas Künemund ,  Holger Sedlak ,  Heinz Söldner

IPC分类号： G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04

摘要： One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is constructed from at least eight transistors, at least four transistors being arranged in a first circuit part and at least four transistors being arranged in a second circuit part and each of the circuit parts having at least two circuit branches.

摘要翻译： 一个实施例提供了具有电连接到比较器单元的第一存储单元的内容可寻址存储单元。 比较器单元由至少八个晶体管构成，至少四个晶体管布置在第一电路部分中，并且至少四个晶体管布置在第二电路部分中，并且每个电路部分具有至少两个电路分支。

公开(公告)号：US5027312A

公开(公告)日：1991-06-25

申请号：US380601

申请日：1989-07-17

申请人： Karl Knauer ,  Winfried Kamp

发明人： Karl Knauer ,  Winfried Kamp

IPC分类号： G06F7/50 ,  G06F7/506 ,  G06F7/507 ,  G06F7/508

CPC分类号： G06F7/507 ,  G06F2207/3876

摘要： A carry-select adder composed of blocks, each containing an input adder cell and a number of adder cells of a first and second type. Each block has one input adder cell interconnected to adder cells of the first and second type which are connected in an alternating fashion. The cells are connected to each other via carry lines and block carry lines. The adder cells of the first and second type each have a gate arrangement which utilizes field effect transistors for transfer, pull-up and pull-down transistors. These transistors are not a component part of a combination gate within an adder cell. The gate arrangement significantly increases the processing speed of the carry-select adder.

摘要翻译： 由块组成的进位选择加法器，每个都包含输入加法器单元和第一和第二类型的加法器单元的数量。 每个块具有互连到第一和第二类型的加法器单元的一个输入加法器单元，以交替方式连接。 单元通过输送线和块输送线相互连接。 第一和第二类型的加法器单元各自具有栅极布置，其利用用于传输，上拉和下拉晶体管的场效应晶体管。 这些晶体管不是加法器单元内的组合门的组成部分。 门排列显着增加了进位选择加法器的处理速度。