公开(公告)号：US07492187B2

公开(公告)日：2009-02-17

申请号：US11437421

申请日：2006-05-19

申请人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

发明人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/1776

摘要： A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

摘要翻译： 用于在FPGA器件中提供配置数据的电路装置包括分配给FGPGA器件的各个可配置逻辑单元的多个输出触发器。 每个输出触发器包括至少一个数据输入和一个数据输出，并且多个输出触发器的第一输出触发器的数据输入可切换地连接到多个输出触发器的第二输出触发器的数据输出 用于通过集成在FPGA器件中的开关器件形成移位寄存器。

公开(公告)号：US07439765B2

公开(公告)日：2008-10-21

申请号：US11437435

申请日：2006-05-19

申请人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

发明人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

IPC分类号： H03K19/173

CPC分类号： H03K19/17748 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/1778 ,  H01L2924/00

摘要： A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors formed on a semiconductor substrate, each of the transistors comprising a controllable path and a control terminal. The controllable paths can be connected in series with one another between a first supply terminal and the output terminal by metallizing first metallization regions. The the transistors of the first set of transistors are arranged on the semiconductor substrate in such a way that at least one controllable path of the transistors can be bridged by metallizing one of the first metallization regions. A respective of the input terminals can be connected to a respective of the control terminals by metallizing a second metallization region.

摘要翻译： 掩模可编程逻辑宏包括至少三个输入端子，输出端子和由形成在半导体衬底上的至少三个晶体管组成的第一组晶体管，每个晶体管包括可控路径和控制端子。 可控路径可以通过金属化第一金属化区域而在第一电源端子和输出端子之间彼此串联连接。 第一组晶体管的晶体管以这样的方式被布置在半导体衬底上，使得可以通过金属化第一金属化区域之一来桥接晶体管的至少一个可控路径。 可以通过金属化第二金属化区域来将各个输入端子连接到相应的控制端子。

公开(公告)号：US20060279329A1

公开(公告)日：2006-12-14

申请号：US11437435

申请日：2006-05-19

申请人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

发明人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/1778 ,  H01L2924/00

摘要： A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors formed on a semiconductor substrate, each of the transistors comprising a controllable path and a control terminal. The controllable paths can be connected in series with one another between a first supply terminal and the output terminal by metallizing first metallization regions. The the transistors of the first set of transistors are arranged on the semiconductor substrate in such a way that at least one controllable path of the transistors can be bridged by metallizing one of the first metallization regions. A respective of the input terminals can be connected to a respective of the control terminals by metallizing a second metallization region.

摘要翻译： 掩模可编程逻辑宏包括至少三个输入端子，输出端子和由形成在半导体衬底上的至少三个晶体管组成的第一组晶体管，每个晶体管包括可控路径和控制端子。 可控路径可以通过金属化第一金属化区域而在第一电源端子和输出端子之间彼此串联连接。 第一组晶体管的晶体管以这样的方式被布置在半导体衬底上，使得可以通过金属化第一金属化区域之一来桥接晶体管的至少一个可控路径。 可以通过金属化第二金属化区域来将各个输入端子连接到相应的控制端子。

公开(公告)号：US20060273823A1

公开(公告)日：2006-12-07

申请号：US11437421

申请日：2006-05-19

申请人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

发明人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/1776

摘要： A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

公开(公告)号：US08854866B2

公开(公告)日：2014-10-07

申请号：US13163131

申请日：2011-06-17

申请人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe ,  Thomas Kuenemund

发明人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe ,  Thomas Kuenemund

IPC分类号： G11C11/00 ,  G06F21/72 ,  H04L9/08

CPC分类号： H04L9/0866 ,  G06F21/72

摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.

摘要翻译： 半导体器件包括识别电路。 识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。 识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。 识别电路还包括用于存储单元的驱动电路。 驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

公开(公告)号：US20120020145A1

公开(公告)日：2012-01-26

申请号：US13163131

申请日：2011-06-17

申请人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe

发明人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe

IPC分类号： G11C11/40 ,  G11C8/08

CPC分类号： H04L9/0866 ,  G06F21/72

摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.

摘要翻译： 半导体器件包括识别电路。 识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。 识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。 识别电路还包括用于存储单元的驱动电路。 驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

公开(公告)号：US20120057411A1

公开(公告)日：2012-03-08

申请号：US12876560

申请日：2010-09-07

申请人： Siegmar Koeppe ,  Winfried Kamp ,  Julie Aunis

发明人： Siegmar Koeppe ,  Winfried Kamp ,  Julie Aunis

IPC分类号： G11C7/10 ,  G11C29/00

CPC分类号： G11C29/10 ,  G11C7/10 ,  G11C11/41 ,  G11C19/28 ,  G11C29/022 ,  G11C29/32

摘要： A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.

摘要翻译： 一种基于锁存器的存储器件包括多个锁存器和一种测试基于锁存器的存储器件的方法，该存储器件包括将锁存器彼此串联连接以形成移位寄存器链。 一个位序列被输入到移位寄存器链中，以通过移位寄存器链来移位比特序列。 输出比特序列并通过移位寄存器链进行移位，并将输入比特序列与输出序列进行比较，以评估第一个测试阶段的锁存器的功能，并测试基于锁存器的存储器件的剩余结构 通过使用例如常规扫描测试方法的第二测试阶段。

公开(公告)号：US20060294178A1

公开(公告)日：2006-12-28

申请号：US11203445

申请日：2005-08-12

申请人： Marc Bernhardt ,  Joel Hatsch ,  Winfried Kamp ,  Siegmar Koeppe

发明人： Marc Bernhardt ,  Joel Hatsch ,  Winfried Kamp ,  Siegmar Koeppe

IPC分类号： G06F7/50

CPC分类号： G06F7/607 ,  G06F7/509 ,  G06F7/5318 ,  G06F2207/3872

摘要： A carry-ripple adder having inputs for supplying three input bits of equal significance 2n that are to be summed and two carry bits of equal significance 2n+1 that are also to be summed. A calculated sum bit of significance 2n and two calculated carry bits of equal significance 2n+1 which are higher than the significance 2n of the sum bit are provided at outputs. A final carry-ripple stage VMA may be used even after a reduction to three bits.

摘要翻译： 具有输入的输入纹波加法器，其具有用于提供要求和的三个等号有效值的输入比特和两个相等重要性的两个进位比特2 n + 1，也是 被总结。 计算出的有效值的和位2＆lt; n＆gt;和两个具有相同重要性的计算的进位位2＆lt; n + 1＆lt; / 2＆gt;其高于 在输出端提供和位。 即使在减少到三位之后，也可以使用最终的进位纹波级VMA。

公开(公告)号：US08331163B2

公开(公告)日：2012-12-11

申请号：US12876560

申请日：2010-09-07

申请人： Siegmar Koeppe ,  Winfried Kamp ,  Julie Aunis

发明人： Siegmar Koeppe ,  Winfried Kamp ,  Julie Aunis

IPC分类号： G11C7/10

CPC分类号： G11C29/10 ,  G11C7/10 ,  G11C11/41 ,  G11C19/28 ,  G11C29/022 ,  G11C29/32

摘要： A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.

摘要翻译： 一种基于锁存器的存储器件包括多个锁存器和一种测试基于锁存器的存储器件的方法，该存储器件包括将锁存器彼此串联连接以形成移位寄存器链。 一个位序列被输入到移位寄存器链中，以通过移位寄存器链来移位比特序列。 输出比特序列并通过移位寄存器链进行移位，并将输入比特序列与输出序列进行比较，以评估第一个测试阶段的锁存器的功能，并测试基于锁存器的存储器件的剩余结构 通过使用例如常规扫描测试方法的第二测试阶段。

公开(公告)号：US08243555B2

公开(公告)日：2012-08-14

申请号：US12187404

申请日：2008-08-07

申请人： Stephan Henzler ,  Siegmar Koeppe

发明人： Stephan Henzler ,  Siegmar Koeppe

IPC分类号： G04F8/00 ,  G04F10/00 ,  H03L7/00 ,  H03H11/26

CPC分类号： G04F10/00 ,  G04F10/005 ,  H03K5/133 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143

摘要： Implementations are presented herein that include a time delay path.

摘要翻译： 这里给出了包括时间延迟路径的实现。