公开(公告)号：US08614720B2

公开(公告)日：2013-12-24

申请号：US13247467

申请日：2011-09-28

申请人： Ock Jin Kim ,  Sang-Gon Lee ,  Yong-Soon Lee ,  Chang Sin Kim

发明人： Ock Jin Kim ,  Sang-Gon Lee ,  Yong-Soon Lee ,  Chang Sin Kim

IPC分类号： G09G5/10

CPC分类号： G09G3/3696 ,  G09G3/2003 ,  G09G3/3614 ,  G09G2310/027 ,  G09G2320/0242 ,  G09G2320/0276 ,  G09G2320/0666

摘要： A display device includes a driving device, which includes a signal controller which receives an input image signal and an input control signal and outputs an image data and a data control signal; a reference voltage generator which generates a first reference voltage and a second reference voltage; and a data driver which receives the image data and the data control signal from the signal controller and outputs a data voltage. The data control signal includes a first color gamma control signal, a second color gamma control signal, and a third color gamma control signal. The data driver includes a reference gamma voltage generator which receives the first reference voltage and the second reference voltage from the reference voltage generator, receives the first color, second color, and third color gamma control signals from the signal controller, and generates a reference gamma voltage according to color information of the image data.

摘要翻译： 显示装置包括：驱动装置，其包括接收输入图像信号的信号控制器和输入控制信号，并输出图像数据和数据控制信号; 参考电压发生器，其产生第一参考电压和第二参考电压; 以及从信号控制器接收图像数据和数据控制信号并输出​​数据电压的数据驱动器。 数据控制信号包括第一颜色伽马控制信号，第二颜色伽马控制信号和第三颜色伽马控制信号。 数据驱动器包括参考伽玛电压发生器，其从参考电压发生器接收第一参考电压和第二参考电压，从信号控制器接收第一颜色，第二颜色和第三颜色伽马控制信号，并产生参考伽马 根据图像数据的颜色信息的电压。

公开(公告)号：US08289261B2

公开(公告)日：2012-10-16

申请号：US12507316

申请日：2009-07-22

申请人： Min-Cheol Lee ,  Yong-Soon Lee

发明人： Min-Cheol Lee ,  Yong-Soon Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G02F1/13454 ,  G09G3/3266 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2360/16 ,  G11C19/28

摘要： A gate driving circuit that may be capable of improving driving margin and maintaining reliability even after long use, and a display device having the gate driving circuit. The gate driving circuit includes a shift register having a plurality of stages dependently connected to one another, wherein each stage includes a pull-up unit outputting a first clock signal as a gate signal in response to a signal of a first node, to which a first input signal is applied, a pull-down unit discharging the gate signal to a gate-off voltage in response to a second input signal, a discharging unit discharging the signal of the first node to the gate-off voltage in response to the second input signal, and a holding unit maintaining the signal of the first node at the gate-off voltage in response to a delay signal of the first clock signal.

摘要翻译： 一种能够在长时间使用后能够提高驱动余量并保持可靠性的栅极驱动电路，以及具有栅极驱动电路的显示装置。 栅极驱动电路包括具有相互依次连接的多个级的移位寄存器，其中每一级包括上拉单元，其响应于第一节点的信号而将第一时钟信号作为门信号输出， 施加第一输入信号，下拉单元响应于第二输入信号将门信号放电到栅极截止电压，放电单元响应于第二输入信号将第一节点的信号放电到栅极截止电压 输入信号和保持单元，其响应于第一时钟信号的延迟信号而将第一节点的信号保持在栅极截止电压。

公开(公告)号：US08243058B2

公开(公告)日：2012-08-14

申请号：US12616604

申请日：2009-11-11

申请人： Jae-Hoon Lee ,  Jun-Yong Song ,  Hoi-Sik Moon ,  Yong-Soon Lee

发明人： Jae-Hoon Lee ,  Jun-Yong Song ,  Hoi-Sik Moon ,  Yong-Soon Lee

IPC分类号： G06F3/038

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

摘要： A gate driving circuit includes a plurality of stages connected to each other. An m-th stage (‘m’ is a natural number) of the stages includes a pull-up part, a pull-down part, a first holding part and a second holding part. The pull-up part outputs a high voltage of a clock signal as a high voltage of an m-th gate signal in response to a high voltage applied to a first output control part. The pull-down part pulls down the high voltage of the m-th gate signal to a first low voltage in response to a high voltage of an (m+1)-th gate signal. The first holding part holds a voltage applied to the first output control part as a second low voltage having a level lower than the first low voltage. The second holding part holds a low voltage of the m-th gate signal to the first low voltage.

摘要翻译： 栅极驱动电路包括彼此连接的多个级。 第m级（“m”是自然数）级包括上拉部分，下拉部分，第一保持部分和第二保持部分。 响应于施加到第一输出控制部分的高电压，上拉部分输出作为第m门信号的高电压的时钟信号的高电压。 下拉部分响应于第（m + 1）门信号的高电压将第m门信号的高电压下拉到第一低电压。 第一保持部分将施加到第一输出控制部分的电压保持为具有低于第一低电压电平的第二低电压。 第二保持部将第m栅极信号的低电压保持为第一低电压。

公开(公告)号：US20120169578A1

公开(公告)日：2012-07-05

申请号：US13212782

申请日：2011-08-18

申请人： Chang-Sin Kim ,  Byeong-Doo Kang ,  Yong-Soon Lee ,  Ock-Jin Kim ,  Sang-Gon Lee

发明人： Chang-Sin Kim ,  Byeong-Doo Kang ,  Yong-Soon Lee ,  Ock-Jin Kim ,  Sang-Gon Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G2300/0413 ,  G09G2310/0232

摘要： A display panel includes a plurality of data lines, a plurality of gate lines, a plurality of dummy loads, a pad portion and a fanout portion. The data lines are disposed in a display area, on which a plurality of pixels are disposed. The gate lines are disposed in the display area and cross the data lines. The dummy loads are disposed in a peripheral area surrounding the display area. The pad portion is disposed in the peripheral area and includes signal pads and dummy pads. The fanout portion includes a first fanout line portion connecting the data lines to the signal pads, and a second fanout line portion connecting the dummy loads to the dummy pads.

摘要翻译： 显示面板包括多条数据线，多条栅极线，多个虚拟负载，焊盘部分和扇出部分。 数据线设置在其上设置有多个像素的显示区域中。 栅极线设置在显示区域中并与数据线交叉。 虚拟负载设置在显示区域周围的周边区域中。 焊盘部分设置在周边区域中，并且包括信号焊盘和虚拟焊盘。 扇出部分包括将数据线连接到信号焊盘的第一扇出线部分和将虚拟负载连接到虚拟焊盘的第二扇出线部分。

公开(公告)号：US20110122117A1

公开(公告)日：2011-05-26

申请号：US12949931

申请日：2010-11-19

申请人： Jae-Hoon Lee ,  Seung-Hwan Moon ,  Yong-Soon Lee ,  Young-Su Kim ,  Chang-Ho Lee ,  Whee-Won Lee ,  Jun-Yong Song ,  Yu-Han Bae

发明人： Jae-Hoon Lee ,  Seung-Hwan Moon ,  Yong-Soon Lee ,  Young-Su Kim ,  Chang-Ho Lee ,  Whee-Won Lee ,  Jun-Yong Song ,  Yu-Han Bae

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/28

摘要： A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

摘要翻译： 显示面板包括非晶硅栅极驱动器，其中比栅极驱动器输出的栅极截止电压更低的电压作为低电压传输信号施加到相邻级。

公开(公告)号：US07808494B2

公开(公告)日：2010-10-05

申请号：US11241211

申请日：2005-09-30

申请人： Yong-Soon Lee ,  Po-Yun Park ,  Nam-Soo Kang ,  Haeng-Won Park ,  Seung-Hwan Moon

发明人： Yong-Soon Lee ,  Po-Yun Park ,  Nam-Soo Kang ,  Haeng-Won Park ,  Seung-Hwan Moon

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G02F1/136286 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0251 ,  G09G2320/0219 ,  G09G2320/0233 ,  H01L27/124

摘要： A display device that employs fewer IC chips and lends itself to cost-efficient manufacturing is presented. The device includes: a plurality of pixel rows including first and second pixels alternately arranged; a plurality of first and second gate lines disposed above and below the pixel rows and applying first and second gate-on voltages to the first and the second pixels, respectively; data lines intersecting the first and the second gate lines, each data line disposed between the first and the second pixels in a pair of first and second pixels and applying data voltages to the first and the second pixels; first and second gate drivers applying the first and the second gate-on voltages to the first and the second gate lines; and a data driver applying the data voltages to the data lines, wherein the second gate-on voltage is applied earlier than the first gate-on voltages by a predetermined time.

摘要翻译： 提出了一种使用更少的IC芯片并适合于经济高效的制造的显示装置。 该装置包括：交替布置的包括第一和第二像素的多个像素行; 多个第一和第二栅极线设置在像素行的上方和下方，分别向第一和第二像素施加第一和第二栅极导通电压; 数据线与第一和第二栅极线相交，每条数据线布置在一对第一和第二像素中的第一和第二像素之间，并将数据电压施加到第一和第二像素; 第一和第二栅极驱动器将第一和第二栅极导通电压施加到第一和第二栅极线; 以及将数据电压施加到数据线的数据驱动器，其中第二栅极导通电压早于第一栅极导通电压施加预定时间。

公开(公告)号：US20100207928A1

公开(公告)日：2010-08-19

申请号：US12616604

申请日：2009-11-11

申请人： Jae-Hoon Lee ,  Jun-Yong Song ,  Hoi-Sik Moon ,  Yong-Soon Lee

发明人： Jae-Hoon Lee ,  Jun-Yong Song ,  Hoi-Sik Moon ,  Yong-Soon Lee

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

摘要： A gate driving circuit includes a plurality of stages connected to each other. An m-th stage (‘m’ is a natural number) of the stages includes a pull-up part, a pull-down part, a first holding part and a second holding part. The pull-up part outputs a high voltage of a clock signal as a high voltage of an m-th gate signal in response to a high voltage applied to a first output control part. The pull-down part pulls down the high voltage of the m-th gate signal to a first low voltage in response to a high voltage of an (m+1)-th gate signal. The first holding part holds a voltage applied to the first output control part as a second low voltage having a level lower than the first low voltage. The second holding part holds a low voltage of the m-th gate signal to the first low voltage.

摘要翻译： 栅极驱动电路包括彼此连接的多个级。 第m级（“m”是自然数）级包括上拉部分，下拉部分，第一保持部分和第二保持部分。 响应于施加到第一输出控制部分的高电压，上拉部分输出作为第m门信号的高电压的时钟信号的高电压。 下拉部分响应于第（m + 1）门信号的高电压将第m门信号的高电压下拉到第一低电压。 第一保持部分将施加到第一输出控制部分的电压保持为具有低于第一低电压电平的第二低电压。 第二保持部将第m栅极信号的低电压保持为第一低电压。

公开(公告)号：US20100141622A1

公开(公告)日：2010-06-10

申请号：US12707639

申请日：2010-02-17

申请人： Dong-Gyu KIM ,  Seung-Hwan Moon ,  Yong-Soon Lee ,  Nam-Soo Kang ,  Haeng-Won Park

发明人： Dong-Gyu KIM ,  Seung-Hwan Moon ,  Yong-Soon Lee ,  Nam-Soo Kang ,  Haeng-Won Park

IPC分类号： G06F3/038

CPC分类号： G02F1/13454 ,  G02F1/1339 ,  G02F1/1345 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78669 ,  H01L29/78678

摘要： Gate-driving circuitry of a thin film transistor array panel is formed on the same plane as a display area of the transistor array panel. The gate-driving circuitry includes driving circuitry and signal lines having apertures. Thus, a sufficient amount of light, even though illuminated from the thin film transistor array panel side, can reach a photosetting sealant overlapping at least in part the gate-driving circuitry. The thin film transistor array panel and the counter panel are put together air-tight and moisture-tight. Consequently, the gate-driving circuitry can avoid corrosion by moisture introduced from outside. Gate-driving circuitry malfunctions can also be reduced.

摘要翻译： 薄膜晶体管阵列面板的栅极驱动电路形成在与晶体管阵列面板的显示区域相同的平面上。 栅极驱动电路包括具有孔径的驱动电路和信号线。 因此，尽管从薄膜晶体管阵列面板侧照明，足够量的光可以到达与栅极驱动电路至少部分重叠的光固化密封剂。 将薄膜晶体管阵列面板和对面板放在一起，气密和防潮。 因此，栅极驱动电路可以避免从外部引入的湿气的腐蚀。 栅极驱动电路故障也可以减少。

公开(公告)号：US20100039363A1

公开(公告)日：2010-02-18

申请号：US12507316

申请日：2009-07-22

申请人： Min-Cheol LEE ,  Yong-Soon LEE

发明人： Min-Cheol LEE ,  Yong-Soon LEE

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G02F1/13454 ,  G09G3/3266 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2360/16 ,  G11C19/28

摘要： A gate driving circuit that may be capable of improving driving margin and maintaining reliability even after long use, and a display device having the gate driving circuit. The gate driving circuit includes a shift register having a plurality of stages dependently connected to one another, wherein each stage includes a pull-up unit outputting a first clock signal as a gate signal in response to a signal of a first node, to which a first input signal is applied, a pull-down unit discharging the gate signal to a gate-off voltage in response to a second input signal, a discharging unit discharging the signal of the first node to the gate-off voltage in response to the second input signal, and a holding unit maintaining the signal of the first node at the gate-off voltage in response to a delay signal of the first clock signal.

摘要翻译： 一种能够在长时间使用后能够提高驱动余量并保持可靠性的栅极驱动电路，以及具有栅极驱动电路的显示装置。 栅极驱动电路包括具有相互依次连接的多个级的移位寄存器，其中每一级包括上拉单元，其响应于第一节点的信号而将第一时钟信号作为门信号输出， 施加第一输入信号，下拉单元响应于第二输入信号将门信号放电到栅极截止电压，放电单元响应于第二输入信号将第一节点的信号放电到栅极截止电压 输入信号和保持单元，其响应于第一时钟信号的延迟信号而将第一节点的信号保持在栅极截止电压。

公开(公告)号：US20090040161A1

公开(公告)日：2009-02-12

申请号：US12145140

申请日：2008-06-24

申请人： Seung-Soo BAEK ,  Yong-Soon LEE ,  Min-Cheol LEE ,  Seong-Young LEE

发明人： Seung-Soo BAEK ,  Yong-Soon LEE ,  Min-Cheol LEE ,  Seong-Young LEE

IPC分类号： G09G3/36

CPC分类号： G09G3/3607 ,  G09G3/3614 ,  G09G3/3659 ,  G09G3/3677 ,  G09G2300/0814 ,  G09G2310/0205 ,  G09G2310/0251 ,  G09G2310/06 ,  G09G2320/0219 ,  G09G2320/0223 ,  G09G2320/0252 ,  G09G2320/0276 ,  G09G2320/028 ,  G11C19/28 ,  H03K5/15093

摘要： A display apparatus includes a panel part having a plurality of gate lines, a plurality of data lines, a plurality of pixels, a data driver and a gate driver part. Each pixel of the plurality of pixels includes a first sub-pixel and a second sub-pixel. The first sub-pixel is connected to a first gate line of the plurality of gate lines and the second sub-pixel is connected to a second gate line of the plurality of gate lines. The first sub-pixel and the second sub-pixel are each commonly connected to one data line of the plurality of data lines. The gate driver part is disposed on the panel part and applies a plurality of gate signals to the plurality of gate lines. A current gate signal of the plurality of gate signals is temporally overlapped with a previous gate signal for a predetermined time interval.

摘要翻译： 显示装置包括具有多条栅极线，多条数据线，多个像素，数据驱动器和栅极驱动器部分的面板部分。 多个像素中的每个像素包括第一子像素和第二子像素。 第一子像素连接到多条栅极线的第一栅极线，第二子像素连接到多条栅极线的第二栅极线。 第一子像素和第二子像素都共同连接到多条数据线中的一条数据线。 栅极驱动器部分设置在面板部分上，并且对多个栅极线施加多个栅极信号。 多个门信号的当前门信号在预定的时间间隔内与先前的门信号暂时重叠。