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    Method for Measuring Display Bond Resistances
    33.
    发明申请
    Method for Measuring Display Bond Resistances 有权
    显示粘结电阻测量方法

    公开(公告)号：US20160202298A1

    公开(公告)日：2016-07-14

    申请号：US14993711

    申请日：2016-01-12

    Applicant: Apple Inc.

    Inventor： Kingsuk Brahma ,  David A. Stronks ,  Hopil Bae ,  Wei H. Yao

    IPC: G01R27/20 ,  G09G3/20

    CPC classification number: G01R27/205 ,  G09G3/006 ,  G09G3/2092 ,  G09G3/2096 ,  G09G3/3607 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2320/0223

    Abstract: A display may have a substrate layer to which a display driver integrated circuit and flexible printed circuit are bonded. The display driver integrated circuit may be provided with switches and control circuitry for controlling the operation of the switches during bond resistance measurements. Test equipment may apply currents to pads in the display driver integrated circuit through contacts in the flexible printed circuit while controlling the switching circuitry. Based on these measurements and the measurement of trace resistances in a dummy flexible printed circuit, the test equipment may determine bond resistances for bonds between the display driver integrated circuit and the display substrate and between the flexible printed circuit and the display substrate. Displays may have master and slave display driver integrated circuits that share coarse reference voltages produced by the master from raw power supply voltages.

    Abstract translation: 显示器可以具有显示驱动器集成电路和柔性印刷电路结合到其上的基板层。 显示驱动器集成电路可以设置有用于在接合电阻测量期间控制开关的操作的开关和控制电路。 测试设备可以通过柔性印刷电路中的触点在显示驱动器集成电路中的焊盘上施加电流，同时控制开关电路。 基于这些测量和虚拟柔性印刷电路中的迹线电阻的测量，测试设备可以确定显示驱动器集成电路和显示器基板之间以及柔性印刷电路和显示器基板之间的结合的结合电阻。 显示器可以具有主从显示驱动器集成电路，其从原始电源电压共享由主机产生的粗参考电压。

    Display driver precharge circuitry
    34.
    发明授权
    Display driver precharge circuitry 有权
    显示驱动器预充电电路

    公开(公告)号：US09318068B2

    公开(公告)日：2016-04-19

    申请号：US14081834

    申请日：2013-11-15

    Applicant: APPLE INC.

    Inventor： David A. Stronks ,  Hopil Bae ,  Kingsuk Brahma ,  Sang Y. Youn

    IPC: G09G3/36

    CPC classification number: G09G3/3696 ,  G09G3/3648 ,  G09G2310/0248 ,  G09G2330/021

    Abstract: Systems and methods for efficiently generating display driver timing signals are provided. In one example, display driver circuitry of an electronic display may provide a negative voltage from a negative voltage supply to display control circuitry during a first period and may provide a positive voltage from a positive voltage supply to the display control circuitry during a second period. After providing the negative voltage during the first period but before providing the positive voltage during the second period, the display driver circuitry may precharge the capacitance of the display control circuitry to ground. In this way, the positive voltage supply substantially does not supply charge to raise the voltage on the capacitance of the display control circuitry from the negative voltage to ground.

    Abstract translation: 提供了有效地产生显示驱动器定时信号的系统和方法。 在一个示例中，电子显示器的显示驱动器电路可以在第一时段期间从负电压源提供负电压到显示控制电路，并且可以在第二时段期间从正电压电源向显示控制电路提供正电压。 在第一时段内提供负电压之后但在第二周期期间提供正电压之前，显示驱动器电路可以将显示控制电路的电容预充电到地。 以这种方式，正电压基本上不提供电荷以将显示控制电路的电容的电压从负电压提升到地。

    DEVICES AND METHODS FOR REDUCING POWER CONSUMPTION OF A DEMULTIPLEXER
    35.
    发明申请
    DEVICES AND METHODS FOR REDUCING POWER CONSUMPTION OF A DEMULTIPLEXER 有权
    用于降低分解器消耗功率的装置和方法

    公开(公告)号：US20140132585A1

    公开(公告)日：2014-05-15

    申请号：US13890928

    申请日：2013-05-09

    Applicant: Apple Inc

    Inventor： Sang Y. Youn ,  Hopil Bae ,  David A. Stronks ,  Kingsuk Brahma ,  Taif A. Syed

    IPC: G09G3/36

    CPC classification number: G09G3/3611 ,  G09G2310/0297 ,  G09G2330/021

    Abstract: The present disclosure relates to devices and methods for reducing power consumption of a display. One electronic display includes a first switch coupled between a first gate of a first transistor and a second gate of a second transistor to selectively connect the first gate to the second gate. The display includes a second switch coupled between the second gate of the second transistor and a third gate of a third transistor to selectively connect the second gate to the third gate. The display also includes driving circuitry that controls the first switch to connect the first gate to the second gate to share a first charge between the first and second gates. The driving circuitry also controls the second switch to connect the second gate to the third gate to share a second charge between the second and third gates. Accordingly, power consumption of the display may be reduced.

    Abstract translation: 本公开涉及用于降低显示器的功耗的装置和方法。 一个电子显示器包括耦合在第一晶体管的第一栅极和第二晶体管的第二栅极之间的第一开关，以选择性地将第一栅极连接到第二栅极。 显示器包括耦合在第二晶体管的第二栅极和第三晶体管的第三栅极之间的第二开关，以选择性地将第二栅极连接到第三栅极。 显示器还包括控制第一开关以将第一栅极连接到第二栅极以共享第一和第二栅极之间的第一电荷的驱动电路。 驱动电路还控制第二开关以将第二栅极连接到第三栅极，以在第二和第三栅极之间共享第二电荷。 因此，可以减少显示器的功耗。

    Systems and methods for external off-time pixel sensing
    36.
    发明授权
    Systems and methods for external off-time pixel sensing 有权

    公开(公告)号：US12136394B2

    公开(公告)日：2024-11-05

    申请号：US16802354

    申请日：2020-02-26

    Applicant: Apple Inc.

    Inventor： Hyunwoo Nho ,  Myungjoon Choi ,  Hyunsoo Kim ,  Mohammad Ali Jangda ,  Jie Won Ryu ,  Shiping Shen ,  Kingsuk Brahma ,  Chaohao Wang ,  Wei H. Yao ,  Alex H. Pai

    IPC: G09G3/3258 ,  G09G3/3233

    Abstract: An electronic device includes a display having multiple regions of pixels. Each pixel includes a diode that emits light based on an amount of current through the diode and a transistor that controls the amount of current flowing through the diode. The electronic device includes driver-integrated circuitry that reduces hysteresis in a first transistor of a first pixel of a region of pixels, settles a threshold voltage of the first transistor, applies a test voltage to the first transistor, and senses a current across the first transistor. The electronic device includes processing circuitry that determines a predetermined voltage based on the current and a predetermined current-voltage relationship determined at an initial temperature, determines a voltage difference between the test voltage and the predetermined voltage, and applies the predetermined voltage and the voltage difference to a second transistor of a second pixel of the region of pixels.

    GLOBAL NONLINEAR SCALER FOR MULTIPLE PIXEL GAMMA RESPONSE COMPENSATION
    39.
    发明公开
    GLOBAL NONLINEAR SCALER FOR MULTIPLE PIXEL GAMMA RESPONSE COMPENSATION 审中-公开

    公开(公告)号：US20240203332A1

    公开(公告)日：2024-06-20

    申请号：US18509592

    申请日：2023-11-15

    Applicant: Apple Inc.

    Inventor： Mario Miscuglio ,  Kingsuk Brahma ,  Jie Won Ryu ,  Shengkui Gao ,  Yuchi Che ,  Graeme M Williams ,  Yi Qiao ,  Wei H Yao ,  Jean-Pierre S Guillou

    IPC: G09G3/3208 ,  G09G3/32

    CPC classification number: G09G3/3208 ,  G09G3/32 ,  G09G2300/0828 ,  G09G2320/0276

    Abstract: In a display characterized by regions with different pixel responses due, for example, to local pixel density variation, voltage-to-luminance matching may be non-universal. Therefore, in order to avoid visual artifacts that may hinder a desired visualization of displayed content, it may be advantageous to compensate the different gamma responses. In some cases, such as with electronic devices having a single pixel density across the display, optical calibration may be performed to determine voltage-to-luminance matching. However, in electronic devices with local pixel density variations, it may be disadvantageous to perform optical calibrations for each region with a different pixel density. Instead of using two distinct gamma curves which may include dedicated optical calibration, a global nonlinear scaler (GNLS) compensation may be applied. Embodiments may pertain to techniques for applying a per-channel and band-global gamma-to-voltage compensation to reduce or minimize a relative luminance error amongst different responses of display regions.

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