公开(公告)号：US09628106B1

公开(公告)日：2017-04-18

申请号：US15007054

申请日：2016-01-26

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/376 ,  H03M3/438

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US09531400B1

公开(公告)日：2016-12-27

申请号：US14932798

申请日：2015-11-04

Applicant: AVNERA CORPORATION

Inventor： Jianping Wen ,  Garry Link ,  Wai Lee

IPC: H03M1/06 ,  H03M1/40 ,  H03M1/44 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.

Abstract translation: 电路可以包括具有第一输入，第二输入和输出的电压比较器Vd; 具有顶板和底板的第一多个电容器Cp [0：n]，其中每个顶板与电压比较器Vd的第一输入电耦合，其中每个顶板也可切换地电耦合到 共模电压Vcm，并且其中每个底板可切换地电耦合在第一输入电压Vinp，参考电压Vref，共模电压Vcm和地之间; 分别具有顶板和底板的第二多个电容器Cn [0：n]，其中每个顶板与电压比较器Vd的第二输入电耦合，其中每个顶板也可切换地电耦合到 共模电压Vcm，并且其中每个底板可切换地电耦合在第二输入电压Vinn，参考电压Vref，共模电压Vcm和地之间; 以及与电压比较器Vd的输出耦合的逐次逼近寄存器（SAR）控制器。

公开(公告)号：US20150195646A1

公开(公告)日：2015-07-09

申请号：US14148533

申请日：2014-01-06

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Wai Lang Lee ,  Jianping Wen

IPC: H04R3/00

CPC classification number: G10K11/178 ,  G10K11/17853 ,  G10K11/17873 ,  G10K11/17875 ,  G10K11/17879 ,  G10K2210/3016 ,  G10K2210/3026 ,  G10K2210/3027 ,  G10K2210/3028 ,  H04R2460/01

Abstract: A programmable Active Noise Compensation (ANC) system for an audio input includes a parameter store structured to store a number of various filter parameters. A mode of operation is selected that represents the type of environment the ANC system is operating in—feed-forward, feed-back, or combined feed-forward and feedback. Different filter parameters are retrieved from the parameter store based on the selected mode and desired operation. Audio inputs are sampled at a relatively high sample rate that matches inputs from a feed-forward and feedback microphone that may be present in the system. Parameters and instructions may be changed in the system responsive to changing conditions of the compensation system.

Abstract translation: 用于音频输入的可编程有源噪声补偿（ANC）系统包括结构化以存储多个滤波器参数的参数存储器。 选择一种操作模式，其表示ANC系统正在进行前馈，反馈或组合的前馈和反馈的环境类型。 基于所选择的模式和期望的操作，从参数存储器检索不同的滤波器参数。 音频输入以相对高的采样率进行采样，该采样率与可能存在于系统中的前馈和反馈麦克风的输入相匹配。 响应于补偿系统的变化条件，可以在系统中改变参数和指令。