公开(公告)号：US20210335742A1

公开(公告)日：2021-10-28

申请号：US16860877

申请日：2020-04-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT

IPC: H01L23/00

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a metal holder. The substrate includes at least one bonding pad disposed adjacent to its surface and the metal holder is disposed adjacent to the bonding pad.

公开(公告)号：US20210202362A1

公开(公告)日：2021-07-01

申请号：US16732149

申请日：2019-12-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a core layer, a conductive interconnect and a semiconductor chip. The core layer has a top surface and a bottom surface opposite to the top surface. The conductive interconnect penetrates through the core layer. The conductive interconnect has a top surface and a bottom surface respectively exposed from the top surface and the bottom surface of the core layer. The semiconductor chip is disposed on the top surface of the core layer. The semiconductor chip includes a conductive pad, and the top surface of the conductive interconnect directly contacts the conductive pad.

公开(公告)号：US20190279924A1

公开(公告)日：2019-09-12

申请号：US15917509

申请日：2018-03-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl APPELT ,  You-Lung YEN

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor package structure includes a first patterned conductive layer including a first conductive pad, a second conductive pad and a first conductive trace disposed between the first conductive pad and the second first conductive pad. The first conductive pad defines a recess. The semiconductor package structure further includes a second patterned conductive layer including a third conductive pad. The semiconductor package structure further includes a first stud bump electrically connecting the first conductive pad of the first patterned conductive layer to the third conductive pad of the second patterned conductive layer. The semiconductor package structure further includes a first encapsulation layer disposed between the first patterned conductive layer and the second patterned conductive layer.

公开(公告)号：US20190088506A1

公开(公告)日：2019-03-21

申请号：US16182589

申请日：2018-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl APPELT ,  Kay Stefan ESSIG ,  William T. CHEN ,  Yuan-Chang SU

IPC: H01L21/56 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes: (1) a first die; (2) conductive pads electrically connected to the first die, and each of the conductive pads having a lower surface; (3) a package body encapsulating the first die and the conductive pads and exposing the lower surface of each of the conductive pads from a lower surface of the package body; and (4) first traces disposed on the lower surface of the package body and connected to the lower surface of each of the conductive pads, wherein a thickness of each of the first traces is less than 100 micrometers.

公开(公告)号：US20180145060A1

公开(公告)日：2018-05-24

申请号：US15359403

申请日：2016-11-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl APPELT ,  Kay Stefan Essig ,  You-Lung Yen

IPC: H01L25/10 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/18 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107

Abstract: A semiconductor package includes a first semiconductor die, a first encapsulant, a first redistribution layer, a second encapsulant and a patterned conductive layer. The first encapsulant encloses the first semiconductor die and has a top surface and a lateral surface. The first redistribution layer is disposed on the top surface of the first encapsulant and electrically connected to the first semiconductor die, wherein a portion of the first redistribution layer is exposed from the lateral surface of the first encapsulant. The second encapsulant covers the first encapsulant and the first redistribution layer. The patterned conductive layer is disposed on at least one of the lateral surface of the first encapsulant or a lateral surface of the second encapsulant, and is electrically connected to the first redistribution layer.