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公开(公告)号：US06820240B2
公开(公告)日：2004-11-16
申请号：US10065201
申请日：2002-09-25
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
摘要翻译： 用于设计集成电路芯片的方法和结构提供芯片设计，并且根据电压要求的相似性和元件的功率状态的时序来分配芯片设计的元件以产生电压岛。 本发明输出包括每个电压岛的功率和定时信息的电压岛规格表; 并自动，无需用户干预，就可以合成电压岛的供电网络。
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公开(公告)号：US06725439B1
公开(公告)日：2004-04-20
申请号：US09678742
申请日：2000-10-04
申请人： Philip S. Homsinger , Andrew D. Huber , Debra K. Korejwa , William J. Livingstone , Jeannie H. Panner , Erich C. Schanzenbach , Douglas W. Stout , Steven H. Voldman , Paul S. Zuchowski
发明人： Philip S. Homsinger , Andrew D. Huber , Debra K. Korejwa , William J. Livingstone , Jeannie H. Panner , Erich C. Schanzenbach , Douglas W. Stout , Steven H. Voldman , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5077
摘要： A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.
摘要翻译： 具有ESD稳健性的集成电路（IC）芯片和IC芯片接线的系统和方法。 每个芯片的I / O端口都应用最小导线宽度和最大电阻约束。 这些限制被传播到设计中。 阵列焊盘连接到位于芯片上的I / O单元。 未使用或浮动焊盘可以直接或通过静电放电（ESD）保护装置连接到电源或接地线。 还包括耦合在电源和接地或返回线路之间的多电源保护装置（ESDxx）。 因此，布线使得ESD保护器件的导线和通孔足够宽，以提供足够的ESD保护。 所有的芯片垫都提供了强大的ESD保护。 然后可以验证设计。
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公开(公告)号：US06292343B1
公开(公告)日：2001-09-18
申请号：US09666632
申请日：2000-09-21
IPC分类号： H02H322
CPC分类号： H01L27/0248
摘要： An ASIC book comprising a gate-array format of ESD components is provided. A customized, optimized and tuned ESD network can be constructed from the ASIC book. Novel ESD circuitry having inter-rail ESD circuitry and single-rail ESD circuitry can be constructed. The inter-rail ESD circuitry is scaleable and comprises one or more diode strings for interconnecting a pair of power rails. The ESD trigger voltage for a diode string is set by the number of diodes within the customized diode string and preferably a sufficient number of diodes are provided within each diode string for power-up and power-down sequence independence. The single-rail ESD circuitry is connected to a level-shifter and may comprise an RC discriminator comprising a customizable plurality of NFET transistors connected in series. The RC discriminator may be connected to a clamping transistor via a buffering circuit, such as an inverter stage, that isolates the gate capacitance of the clamping transistor from the RC discriminator. In a second aspect of the invention an ASIC book comprising a gate-array format of ESD components is provided. A customized, optimized and tuned ESD network can be constructed from the ASIC book.
摘要翻译： 提供了一种包括ESD组件的门阵列格式的ASIC书。 可以通过ASIC书籍构建定制，优化和调优的ESD网络。 可以构建具有轨间ESD电路和单轨ESD电路的新型ESD电路。 轨间ESD电路是可扩展的，并且包括用于互连一对电源轨的一个或多个二极管串。 二极管串的ESD触发电压由定制二极管串中的二极管的数量设定，并且优选地，在每个二极管串内提供足够数量的二极管用于上电和断电序列独立性。 单轨ESD电路连接到电平转换器，并且可以包括RC鉴频器，RC鉴频器包括串联连接的可定制的多个NFET晶体管。 RC鉴频器可以经由缓冲电路（例如逆变器级）连接到钳位晶体管，该缓冲电路将钳位晶体管的栅极电容与RC鉴别器隔离。在本发明的第二方面，ASIC书籍包括栅极阵列 提供了ESD组件的格式。 可以通过ASIC书籍构建定制，优化和调优的ESD网络。
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公开(公告)号：US06262873B1
公开(公告)日：2001-07-17
申请号：US09657081
申请日：2000-09-07
IPC分类号： H02H322
CPC分类号： H01L27/0248
摘要： A method for automatically generating a custom ESD network for an integrated circuit is provided. When a user provides chip size and chip capacitance for the integrated circuit, components for the customized ESD network are automatically selected based on the user-provided chip size and chip capacitance and the adequacy of the ESD behavior of an ESD network employing the selected components is evaluated.
摘要翻译： 提供了一种用于自动生成用于集成电路的定制ESD网络的方法。 当用户为集成电路提供芯片尺寸和芯片电容时，根据用户提供的芯片尺寸和芯片电容自动选择定制ESD网络的组件，并且使用所选组件的ESD网络的ESD行为是否合适 评估。
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公开(公告)号：US5151619A
公开(公告)日：1992-09-29
申请号：US595911
申请日：1990-10-11
申请人： John S. Austin , Ronald A. Piro , Douglas W. Stout
发明人： John S. Austin , Ronald A. Piro , Douglas W. Stout
IPC分类号： H01L27/092 , H01L21/8238 , H03K19/003 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/00315 , H03K19/0948
摘要： A CMOS off-chip driver circuit is provided which includes a P-channel pull up transistor and an N-channel pull down transistor serially arranged between a first voltage source having a supply voltage of a given magnitude and ground with the common point between the transistors forming an output terminal to which is connected a circuit including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. A first P-channel field effect transistor is connected between the output terminal and the gate electrode of the pull up transistor. A first input terminal is coupled to the gate electrode of the pull up transistor through a transmission gate including a first N-channel field effect transistor arranged in parallel with a second P-channel field effect transistor, with a gate electrode of the first N-channel transistor being connected to the first voltage source and the gate electrode of the second P-channel transistor being connected to the output terminal.
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公开(公告)号：US08015526B2
公开(公告)日：2011-09-06
申请号：US12138871
申请日：2008-06-13
申请人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
发明人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译： 公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。 在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。 瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。 使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。
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37.发明授权Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices 失效用于集成电路器件实现基于氧化物泄漏的分压网络的设计结构公开(公告)号：US07579897B2
公开(公告)日：2009-08-25
申请号：US11872743
申请日：2007-10-16
IPC分类号： H03K17/687
CPC分类号： H03K17/687 , H03K2017/6878
摘要： A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configured to have an input voltage coupled thereacross; and at least one of a source of the FET and a drain of the FET configured to have an output voltage taken therefrom; wherein the output voltage represents a divided voltage with respect to the input voltage.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括分压器件，其包括具有第一栅极的双栅场效应晶体管（FET）和设置在体区相对侧的第二栅极; 所述第一和第二栅极配置成具有耦合到其上的输入电压; 并且所述FET的源极和所述FET的漏极中的至少一个被配置为具有从其获取的输出电压; 其中输出电压表示相对于输入电压的分压。
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38.发明申请公开(公告)号：US20090101940A1
公开(公告)日：2009-04-23
申请号：US11874957
申请日：2007-10-19
CPC分类号： H03K19/1778 , H01L29/785 , H01L29/78648
摘要： A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell area. The conductivity and drive strength of the dual gate device may be selectively tuned through independent processing of manufacturing parameters to provide an asymmetric circuit response for the device or a symmetric response as dictated by the circuit application.
摘要翻译： 适用于标准单元设计方法的门阵列单元或包括双栅极FET器件的可编程门阵列，以在相同单元单元区域内提供一系列性能选项。 可以通过制造参数的独立处理来选择性地调节双栅极器件的导电性和驱动强度，以为器件提供不对称电路响应或由电路应用所指示的对称响应。
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公开(公告)号：US07474124B2
公开(公告)日：2009-01-06
申请号：US11684890
申请日：2007-03-12
IPC分类号： H03K17/16
CPC分类号： H03K19/09429
摘要： The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus (one bit of data per bus line or wire). The bus keeper and logic control circuit is maintained in isolation from I/O functional driver and is responsive to a tri-state signal (TS), normally provided by the IC or SOC, or the I/O circuit during normal I/O receiver side operation. The inventive bus keeper and logic circuit selectively enables any of a tri-state state, a pull-up state, pull-down state and bus keep mode state at the driver output pad in the presence of the tri-state enable signal, and is disabled when the I/O bus drive buffer circuit is in drive mode.
摘要翻译： 这里的发明涉及用于与I / O电路一起使用的本发明的总线保持器和逻辑电路，例如用于I / O缓冲器电路的接收器侧。 本发明的电路将IC功能的一条数据线连接到三态总线的一条线路（每总线或线路的一位数据）。 母线保护器和逻辑控制电路与I / O功能驱动器保持隔离，并且响应于通常由IC或SOC提供的三态信号（TS）或正常I / O接收器中的I / O电路 侧面操作。 本发明的总线保持器和逻辑电路在存在三态使能信号的情况下，有选择地使驱动器输出焊盘处于三状态，上拉状态，下拉状态和总线保持模式状态，并且是 当I / O总线驱动缓冲电路处于驱动模式时禁用。
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公开(公告)号：US07454305B2
公开(公告)日：2008-11-18
申请号：US11164040
申请日：2005-11-08
CPC分类号： G01R31/2884 , G01R35/005
摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.
摘要翻译： 公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。 通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在各个芯片内的存储装置上。 然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。 内插值与芯片在efuse控制文件中的坐标一起被记录。 这样的信息随后被存储在芯片内的efuse模块中。 片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。
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