公开(公告)号：US06252911B1

公开(公告)日：2001-06-26

申请号：US09096062

申请日：1998-06-11

申请人： Alan Gatherer ,  Murtaza Ali

发明人： Alan Gatherer ,  Murtaza Ali

IPC分类号： H04L512

CPC分类号： H04L25/4927

摘要： A trellis shaping method is described that may be used for suppressing DC components and/or Nyquist frequency components from the outputs of a PCM (56K) modem. The technique is based on convolutional codes. The code is generated through the use of a Viterbi decoder. Data bits are mapped for transmission into a set of n magnitudes and (n−k) sign bits s. The sign bits s are passed through (HT)−1 to get preliminary sing bits t=s (HT)−1 of size n. (HT)−1 is a matrix of size (n−k) by n which represents the left inverse of the syndrome-former matrix HT of convolutional code c=b G, defined so that G HT=0. The convolutional code is then added to sign bits t through an XOR operation to give final sign bits s (HT)−1+b G. After transmission, the final sign bits are passed through HT to give an output of (s (HT)−1+b G) (HT))=s, for recovery of the data bits.

摘要翻译： 描述了可用于从PCM（56K）调制解调器的输出抑制DC分量和/或奈奎斯特频率分量的网格整形方法。 该技术基于卷积码。 该代码通过使用维特比解码器生成。 映射数据位以传输到一组n个幅度和（n-k）个符号位。 符号位通过（HT）-1，以获得大小为n的初步字位t = s（HT）-1。 （HT）-1是大小（n-k）乘以n的矩阵，其表示卷积码c = b G的综合征 - 形成矩阵HT的左倒数，使得G HT = 0。 然后通过XOR操作将卷积码添加到符号位t，以得到最终符号位s（HT）-1 + b G。传输后，最终符号位通过HT，输出（s（HT） -1 + b G）（HT））= s，用于恢复数据位。

公开(公告)号：US5889691A

公开(公告)日：1999-03-30

申请号：US782001

申请日：1997-01-06

申请人： Alan Gatherer ,  Carl E. Lemonds

发明人： Alan Gatherer ,  Carl E. Lemonds

IPC分类号： G06F7/52

CPC分类号： G06F7/5272

摘要： In a multiplier unit having a preprocessor stage, a multiplier stage, and a summation stage, the multiplier stage includes a shift register, a gate component for controllably transmitting the multiplicand A in a manner determined by a bit signal of multiplier B applied to the gate component control terminal. Partial products are grouped by multiplicand digits and each digit is applied, through delay components determined by the order of the digit, to first terminals of an associated adder components. Output signals from each adder component is transmitted through a plurality of delay components and applied to second input terminals of the same adder component. In this manner, partial products A.sub.p *B.sub.q are assembled and the partial products (A.sub.0 + . . . A.sub.M)*B.sub.q =A*B.sub.q can be applied to the summation unit in a single period. When the multiplier is an integer multiple of the multiplicand, the implementation is particularly convenient.

摘要翻译： 在具有预处理器级，乘法器级和求和级的乘法器单元中，乘法器级包括移位寄存器，用于以由施加到门的乘法器B的位信号确定的方式可控地发送被乘数A的门分量 组件控制终端。 部分产品按被乘数分组，每个数字通过由数字顺序确定的延迟分量应用于相关加法器分量的第一个终端。 来自每个加法器分量的输出信号通过多个延迟分量传输并被施加到相同加法器分量的第二输入端。 以这种方式，部分乘积Ap * Bq被组装，并且部分乘积（A0 +。。AM）* Bq = A * Bq可以在单个周期内应用于求和单元。 当乘数是被乘数的整数倍时，实现特别方便。

公开(公告)号：US5461640A

公开(公告)日：1995-10-24

申请号：US253471

申请日：1994-06-03

申请人： Alan Gatherer

发明人： Alan Gatherer

IPC分类号： H04L25/03 ,  H03H7/30

CPC分类号： H04L25/03133

摘要： The present invention includes an optimized equalizer (22) used to equalize a signal (at 20) received from a distorting channel (18). First, auto and cross correlations of a predetermined training sequence and the received signal are generated (at 21c). The correlations are then used to generate a solution matrix (21d). An eigenvector associated with a maximum eigenvalue of a function of the correlations is formed (21e) using the solution matrix (21d) and then used to generate equalizer control signals (21f) or parameters defining taps of a filter implementing the equalizer (22).

摘要翻译： 本发明包括用于均衡从失真信道（18）接收的信号（在20）的优化均衡器（22）。 首先，生成预定训练序列与接收信号的自相关和交叉相关（21c）。 然后使用相关性来生成解矩阵（21d）。 使用解矩阵（21d）形成与相关函数的最大特征值相关联的特征向量（21e），然后用于产生均衡器控制信号（21f）或定义实现均衡器（22）的滤波器的抽头的参数。

公开(公告)号：US08396058B2

公开(公告)日：2013-03-12

申请号：US13101692

申请日：2011-05-05

申请人： Stephen J. Perkins ,  Alan Gatherer ,  Krishnasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

发明人： Stephen J. Perkins ,  Alan Gatherer ,  Krishnasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

IPC分类号： H04L12/66

CPC分类号： H04L41/08 ,  H04L29/06027 ,  H04L41/0206 ,  H04L41/024 ,  H04L41/12 ,  H04L45/00 ,  H04L45/24 ,  H04L45/56 ,  H04L47/2416 ,  H04L65/105 ,  H04L65/4076 ,  H04L65/602 ,  H04L65/605 ,  H04L65/80 ,  H04L67/14 ,  H04L69/40 ,  H04W28/04 ,  H04W40/02 ,  H04W40/20 ,  H04W40/246 ,  H04W84/042 ,  H04W88/08 ,  H04W88/14 ,  H04W88/16

摘要： In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105). Other forms of the invention encompass other processes, improved packets and packet ensembles (111,113), integrated circuits (610), chipsets (DSP 1721, MCU), computer cards (1651), information storage articles (1511,1611), systems, computers (103,105), gateways (191,193), routers (131,133), cellular telephone handsets (181,189), wireless base stations (183,187), appliances (1721,1731,1741), and packet networks (100), and other forms as disclosed and claimed.

摘要翻译： 在本发明的一种形式中，发送计算机（103）将实时信息发送到分组网络（100）耦合到发送方计算机（103）的接收机（105）的过程，其中分组（111,113）有时 包括将包含来自发送者计算机（103）的实时信息的分组（441）通过分组网络（100）中的至少一个路径（119）引导到接收机计算机（105）的步骤， 以及将分组网络（100）中的至少一个路径分集路径（117）包含取决于来自发送者计算机（103）的实时信息的信息的分组（113）导向到同一接收机计算机（105）。 本发明的其他形式包括其他过程，改进的分组和分组集合（111,113），集成电路（610），芯片组（DSP1721，MCU），计算机卡（1651），信息存储产品（1511,1611），系统，计算机 （103,105），网关（191,193），路由器（131,133），蜂窝电话手机（181,189），无线基站（183,187），设备（1721,1731,1741）和分组网络（100） 声称。

公开(公告)号：US20110211573A1

公开(公告)日：2011-09-01

申请号：US13101692

申请日：2011-05-05

申请人： Stephen J. Perkins ,  Alan Gatherer ,  Krishanasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

发明人： Stephen J. Perkins ,  Alan Gatherer ,  Krishanasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

IPC分类号： H04L12/66

CPC分类号： H04L41/08 ,  H04L29/06027 ,  H04L41/0206 ,  H04L41/024 ,  H04L41/12 ,  H04L45/00 ,  H04L45/24 ,  H04L45/56 ,  H04L47/2416 ,  H04L65/105 ,  H04L65/4076 ,  H04L65/602 ,  H04L65/605 ,  H04L65/80 ,  H04L67/14 ,  H04L69/40 ,  H04W28/04 ,  H04W40/02 ,  H04W40/20 ,  H04W40/246 ,  H04W84/042 ,  H04W88/08 ,  H04W88/14 ,  H04W88/16

摘要： In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105). Other forms of the invention encompass other processes, improved packets and packet ensembles (111,113), integrated circuits (610), chipsets (DSP 1721, MCU), computer cards (1651), information storage articles (1511,1611), systems, computers (103,105), gateways (191,193), routers (131,133), cellular telephone handsets (181,189), wireless base stations (183,187), appliances (1721,1731,1741), and packet networks (100), and other forms as disclosed and claimed.

摘要翻译： 在本发明的一种形式中，发送计算机（103）将实时信息发送到分组网络（100）耦合到发送方计算机（103）的接收机（105）的过程，其中分组（111,113）有时 包括将包含来自发送者计算机（103）的实时信息的分组（441）通过分组网络（100）中的至少一个路径（119）引导到接收机计算机（105）的步骤， 以及将分组网络（100）中的至少一个路径分集路径（117）包含取决于来自发送者计算机（103）的实时信息的信息的分组（113）导向到同一接收机计算机（105）。 本发明的其他形式包括其他过程，改进的分组和分组集合（111,113），集成电路（610），芯片组（DSP1721，MCU），计算机卡（1651），信息存储产品（1511,1611），系统，计算机 （103,105），网关（191,193），路由器（131,133），蜂窝电话手机（181,189），无线基站（183,187），设备（1721,1731,1741）和分组网络（100） 声称。

公开(公告)号：US07693062B2

公开(公告)日：2010-04-06

申请号：US11175411

申请日：2005-07-06

申请人： Stephen J. Perkins ,  Alan Gatherer ,  Krishanasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

发明人： Stephen J. Perkins ,  Alan Gatherer ,  Krishanasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

IPC分类号： G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26

CPC分类号： H04L41/08 ,  H04L29/06027 ,  H04L41/0206 ,  H04L41/024 ,  H04L41/12 ,  H04L45/00 ,  H04L45/24 ,  H04L45/56 ,  H04L47/2416 ,  H04L65/105 ,  H04L65/4076 ,  H04L65/602 ,  H04L65/605 ,  H04L65/80 ,  H04L67/14 ,  H04L69/40 ,  H04W28/04 ,  H04W40/02 ,  H04W40/20 ,  H04W40/246 ,  H04W84/042 ,  H04W88/08 ,  H04W88/14 ,  H04W88/16

摘要： In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105). Other forms of the invention encompass other processes, improved packets and packet ensembles (111,113), integrated circuits (610), chipsets (DSP 1721, MCU), computer cards (1651), information storage articles (1511,1611), systems, computers (103,105), gateways (191,193), routers (131,133), cellular telephone handsets (181,189), wireless base stations (183,187), appliances (1721,1731,1741), and packet networks (100), and other forms as disclosed and claimed.

摘要翻译： 在本发明的一种形式中，发送计算机（103）将实时信息发送到分组网络（100）耦合到发送方计算机（103）的接收机（105）的过程，其中分组（111,113）有时 包括将包含来自发送者计算机（103）的实时信息的分组（441）通过分组网络（100）中的至少一个路径（119）引导到接收机计算机（105）的步骤， 以及将分组网络（100）中的至少一个路径分集路径（117）包含取决于来自发送者计算机（103）的实时信息的信息的分组（113）导向到同一接收机计算机（105）。 本发明的其他形式包括其他过程，改进的分组和分组集合（111,113），集成电路（610），芯片组（DSP1721，MCU），计算机卡（1651），信息存储产品（1511,1611），系统，计算机 （103,105），网关（191,193），路由器（131,133），蜂窝电话手机（181,189），无线基站（183,187），设备（1721,1731,1741）和分组网络（100） 声称。

公开(公告)号：US07400608B2

公开(公告)日：2008-07-15

申请号：US11032985

申请日：2005-01-11

申请人： Aris Papasakellariou ,  Alan Gatherer

发明人： Aris Papasakellariou ,  Alan Gatherer

IPC分类号： H04B1/00

CPC分类号： H04B1/7107

摘要： The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator, delay devices, correlators or matched filters (MF), spreading circuits and subtracting and adding devices. The IC process in accordance with the invention includes using a bank of MF to despread the received signal at every time instant corresponding to every identified multipath of every user's transmitted signal. Based on the despread signals, an initial decision for the present information symbol of every user can be made using a single-user receiver such as, for example, the conventional Rake receiver or an equalizer. Based on the initial decisions, IC regenerates the multipath signals for each user using timed versions of the spread spectrum code, the delays of the multipaths, and the corresponding channel medium estimates. By adding the regenerated signal estimates for the multipaths of all users, an estimate of the received signal at the input of the receiver prior to despreading can be reconstructed. Each IC unit despreads the regenerated received signal using timed versions of the corresponding spread spectrum code for each multipath delay. The result is subsequently subtracted from the initial despread signal and, to avoid removing the desired user path component, the reconstructed, interference-free, desired despread signal path is also added. The above IC process may be repeated several times (e.g., using several IC stages). Performing interference cancellation after despreading the regenerated estimate of the received signal leads to substantially smaller complexity than the prior art approach where the interference cancellation occurs prior to dispreading.

摘要翻译： 干扰消除（IC）系统（500）包括应用IC的多个IC单元。 每个IC单元具有其扩频码发生器，延迟器件，相关器或匹配滤波器（MF），扩展电路以及减法和加法器件。 根据本发明的IC过程包括使用一组MF来在对应于每个用户发送的信号的每个所识别的多路径的每个时刻解扩展所接收的信号。 基于解扩信号，可以使用例如常规Rake接收机或均衡器的单用户接收机来对每个用户的当前信息符号进行初始判定。 基于初始决定，IC使用扩展频谱码的定时版本，多路径的延迟以及相应的信道介质估计来为每个用户再生多径信号。 通过添加所有用户的多路径的再生信号估计，可以重构在解扩之前在接收机的输入处的接收信号的估计。 每个IC单元使用用于每个多径延迟的相应扩频码的定时版本对再生的接收信号进行解扩。 随后从初始解扩展信号中减去结果，为了避免去除所需的用户路径分量，也添加了重建的，无干扰的期望解扩信号路径。 上述IC过程可以重复几次（例如，使用几个IC级）。 在解扩接收信号的再生估计之后执行干扰消除导致比在分散之前发生干扰消除的现有技术方法显着更小的复杂度。

公开(公告)号：US06904106B2

公开(公告)日：2005-06-07

申请号：US09974576

申请日：2001-10-09

申请人： Aris Papasakellariou ,  Alan Gatherer

发明人： Aris Papasakellariou ,  Alan Gatherer

IPC分类号： H04B1/707 ,  H04L27/06

CPC分类号： H04B1/7107

摘要： The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator, delay devices, correlators or matched filters (MF), spreading circuits and subtracting and adding devices. The IC process in accordance with the invention includes using a bank of MF to despread the received signal at every time instant corresponding to every identified multipath of every user's transmitted signal. Based on the despread signals, an initial decision for the present information symbol of every user can be made using a single-user receiver such as, for example, the conventional Rake receiver or an equalizer. Based on the initial decisions, IC regenerates the multipath signals for each user using timed versions of the spread spectrum code, the delays of the multipaths, and the corresponding channel medium estimates. By adding the regenerated signal estimates for the multipaths of all users, an estimate of the received signal at the input of the receiver prior to despreading can be reconstructed. Each IC unit despreads the regenerated received signal using timed versions of the corresponding spread spectrum code for each multipath delay. The result is subsequently subtracted from the initial despread signal and, to avoid removing the desired user path component, the reconstructed, interference-free, desired despread signal path is also added. The above IC process may be repeated several times (e.g., using several IC stages). Performing interference cancellation after despreading the regenerated estimate of the received signal leads to substantially smaller complexity than the prior art approach where the interference cancellation occurs prior to dispreading.

摘要翻译： 干扰消除（IC）系统（500）包括应用IC的多个IC单元。 每个IC单元具有其扩频码发生器，延迟器件，相关器或匹配滤波器（MF），扩展电路以及减法和加法器件。 根据本发明的IC过程包括使用一组MF来在对应于每个用户发送的信号的每个所识别的多路径的每个时刻解扩展所接收的信号。 基于解扩信号，可以使用例如常规Rake接收机或均衡器的单用户接收机来对每个用户的当前信息符号进行初始判定。 基于初始决定，IC使用扩展频谱码的定时版本，多路径的延迟以及相应的信道介质估计来为每个用户再生多径信号。 通过添加所有用户的多路径的再生信号估计，可以重构在解扩之前在接收机的输入处的接收信号的估计。 每个IC单元使用用于每个多径延迟的相应扩频码的定时版本对再生的接收信号进行解扩。 随后从初始解扩展信号中减去结果，为了避免去除所需的用户路径分量，也添加了重建的，无干扰的期望的解扩信号路径。 上述IC过程可以重复几次（例如，使用几个IC级）。 在解扩接收信号的再生估计之后执行干扰消除导致比在分散之前发生干扰消除的现有技术方法显着更小的复杂度。

公开(公告)号：US06690750B1

公开(公告)日：2004-02-10

申请号：US09471430

申请日：1999-12-23

申请人： Dale E. Hocevar ,  Alan Gatherer

发明人： Dale E. Hocevar ,  Alan Gatherer

IPC分类号： H03D100

CPC分类号： H03M13/6502 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6569

摘要： A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and communicate the identified path decisions to a next ACS stage coupled thereto. A Traceback unit is provided for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory.

摘要翻译： 根据本发明提供维特比解码器系统。 解码器系统包括状态度量更新单元，其包括状态度量存储器和级联的加法/比较/选择（ACS）单元。 级联的ACS单元包括多个串联耦合的ACS级，用于结合状态度量存储器执行多个ACS操作。 ACS阶段可操作以识别多个路径决策，并将所识别的路径决定传递到与其耦合的下一个ACS阶段。 提供追溯单元用于在与之相关联的回溯存储器中存储一组累积的路径决策，并且对该组累积的路径决定执行回溯。 与ACS阶段和下一个ACS阶段相关联的路径决策在被写入回溯存储器之前在ACS操作期间作为集合被累积，从而最小化对回溯存储器的访问。

公开(公告)号：US06603412B2

公开(公告)日：2003-08-05

申请号：US10033135

申请日：2001-12-28

申请人： Alan Gatherer ,  Anand Dabak ,  Timothy M. Schmidl ,  John Linn

发明人： Alan Gatherer ,  Anand Dabak ,  Timothy M. Schmidl ,  John Linn

IPC分类号： H03M700

CPC分类号： H03M13/6566 ,  H03M13/271 ,  H03M13/2771

摘要： Quasi-parallel read/write interleaver architecture for data blocks by sequential spreading of variable size data subblocks into memory banks with bank address contention initiating the next data subblock. Iterative Turbo decoders with MAP decoders use such quasi-parallel interleavers and deinterleavers.

摘要翻译： 用于数据块的准并行读/写交织器架构通过将可变大小的数据子块顺序扩展到具有启动下一数据子块的存储体地址争用的存储体。 具有MAP解码器的迭代Turbo解码器使用这种准并行交织器和解交织器。