公开(公告)号：US10884811B2

公开(公告)日：2021-01-05

申请号：US15870764

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20200273424A1

公开(公告)日：2020-08-27

申请号：US16587582

申请日：2019-09-30

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  James S. Ismail ,  Keith Cox ,  Gaurav Kapoor

IPC: G09G5/00 ,  G06F1/26 ,  G06T1/20 ,  G09G5/18 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/60

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

公开(公告)号：US10431181B2

公开(公告)日：2019-10-01

申请号：US15471553

申请日：2017-03-28

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  James S. Ismail ,  Keith Cox ,  Gaurav Kapoor

IPC: G06F5/00 ,  G06F1/26 ,  G09G5/00 ,  G06T1/20 ,  G09G5/18 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/60 ,  G06F1/20 ,  G06T13/80

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

公开(公告)号：US10417054B2

公开(公告)日：2019-09-17

申请号：US15870763

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/26 ,  G06F9/38 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/30 ,  G06F1/3206

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20180349182A1

公开(公告)日：2018-12-06

申请号：US15870766

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20180349175A1

公开(公告)日：2018-12-06

申请号：US15870760

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/26 ,  G06F9/50 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US09613393B2

公开(公告)日：2017-04-04

申请号：US14821665

申请日：2015-08-07

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  James S. Ismail ,  Keith Cox ,  Gaurav Kapoor

IPC: G06F1/20 ,  G06F1/32 ,  G06T1/20 ,  G09G5/00 ,  G09G5/18 ,  G06F1/26

CPC classification number: G09G5/003 ,  G06F1/20 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T2200/28 ,  G09G5/18 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/127 ,  Y02D10/126 ,  Y02D10/172

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

公开(公告)号：US09477998B2

公开(公告)日：2016-10-25

申请号：US14489356

申请日：2014-09-17

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  Keith Cox ,  Cyril de la Cropte de Chanterac ,  Karl D. Vulkan

IPC: G06T15/00 ,  G06T1/20 ,  G06T13/80 ,  G09G5/18

CPC classification number: G06T1/20 ,  G06T13/80 ,  G09G5/18 ,  G09G5/363 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2340/045

Abstract: The embodiments set forth a technique for targeted scaling of the voltage and/or frequency of hardware components included in a mobile computing device. One embodiment involves independently analyzing the individual frame rates of each animation within a user interface (UI) of a mobile computing device instead of analyzing the frame rate of the UI as a whole. This can involve establishing, for each animation being displayed within the UI, a corresponding performance control pipeline that generates a control signal for scaling a performance mode of the hardware components (e.g., a Central Processing Unit (CPU)) included in the mobile computing device. In this manner, the control signals generated by the performance control pipelines can be aggregated to produce a control signal that causes a power management component to scale the performance mode(s) of the hardware components.

Abstract translation: 这些实施例提出了用于针对包括在移动计算设备中的硬件组件的电压和/或频率进行目标缩放的技术。 一个实施例涉及独立地分析移动计算设备的用户界面（UI）内的每个动画的各个帧速率，而不是分析整个UI的帧速率。 这可以涉及为在UI内显示的每个动画建立相应的性能控制流水线，其生成用于缩放包括在移动计算设备中的硬件组件（例如，中央处理单元（CPU））的性能模式的控制信号 。 以这种方式，可以聚合由性能控制管线产生的控制信号，以产生控制信号，该控制信号使得功率管理部件缩放硬件部件的性能模式。