公开(公告)号：US11468945B2

公开(公告)日：2022-10-11

申请号：US17071449

申请日：2020-10-15

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Joel Thornton Irby ,  Andy Wangkun Chen

IPC: G11C11/418 ,  G11C11/419

Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.

公开(公告)号：US20220122655A1

公开(公告)日：2022-04-21

申请号：US17071449

申请日：2020-10-15

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Joel Thornton Irby ,  Andy Wangkun Chen

IPC: G11C11/418 ,  G11C11/419

Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.

公开(公告)号：US10854280B2

公开(公告)日：2020-12-01

申请号：US15691001

申请日：2017-08-30

Applicant: ARM Limited

Inventor： Abhairaj Singh ,  Vivek Asthana ,  Monu Rathore ,  Ankur Goel ,  Nikhil Kaushik ,  Rachit Ahuja ,  Rahul Mathur ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C11/408 ,  G11C11/419 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

公开(公告)号：US10535386B2

公开(公告)日：2020-01-14

申请号：US15603252

申请日：2017-05-23

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Rahul Mathur ,  Abhishek Baradia ,  Hsin-Yu Chen

IPC: G11C8/06 ,  G11C8/10

Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.