公开(公告)号：US20130009277A1

公开(公告)日：2013-01-10

申请号：US13617576

申请日：2012-09-14

申请人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

发明人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/06

CPC分类号： H01L29/945 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/66181

摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

摘要翻译： 公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。 该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。 该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

公开(公告)号：US08338279B2

公开(公告)日：2012-12-25

申请号：US13075450

申请日：2011-03-30

申请人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

发明人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

IPC分类号： H01L21/20

CPC分类号： H01L21/823425 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/823412 ,  H01L22/12 ,  H01L22/34 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.

摘要翻译： 提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。 第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。 第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。 第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。

公开(公告)号：US20110316046A1

公开(公告)日：2011-12-29

申请号：US12825791

申请日：2010-06-29

申请人： Kevin K. Chan ,  Abhishek Dube ,  Eric C. Harley ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman ,  Linda R. Black

发明人： Kevin K. Chan ,  Abhishek Dube ,  Eric C. Harley ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman ,  Linda R. Black

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684

摘要： A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.

摘要翻译： 一种用于形成场效应晶体管器件的方法，包括：在衬底上形成栅极叠层部分，在栅堆叠部分和衬底的一部分上形成间隔部分，去除衬底的暴露部分，将第一硅材料外延生长 衬底的暴露部分，去除外延生长的第一硅材料的一部分以暴露衬底的第二部分，以及在衬底的暴露的第二部分和第一硅材料上外延生长第二硅材料。

公开(公告)号：US20110162875A1

公开(公告)日：2011-07-07

申请号：US12683857

申请日：2010-01-07

申请人： Tien-Jen Cheng ,  Abhishek Dube ,  Zhengwen Li ,  Huilong Zhu

发明人： Tien-Jen Cheng ,  Abhishek Dube ,  Zhengwen Li ,  Huilong Zhu

IPC分类号： H05K1/09 ,  B05D5/12

CPC分类号： H01L21/76834 ,  H01L21/76826 ,  H01L21/76832 ,  H05K3/282 ,  H05K3/388 ,  H05K3/4682

摘要： A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer.

摘要翻译： 金属互连结构在含铜结构中的铜原子和自对准铜封装层之间提供高粘合强度，其仅选择性地沉积在暴露的铜表面上。 下层金属互连结构包括第一介电材料层和嵌入在下金属衬里中的含铜结构。 在形成含铜结构的平坦化工艺之后，将含铜结构体的露出表面形成Cu-S键的材料施加到含铜结构体的表面。 该材料仅选择性地沉积在暴露的Cu表面上，从而形成自对准的铜封装层，并且对下面的铜表面提供高粘附强度。 随后可以在铜封装层上形成电介质盖层和上层金属互连结构。

公开(公告)号：US20110095343A1

公开(公告)日：2011-04-28

申请号：US12607104

申请日：2009-10-28

申请人： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.

摘要翻译： 公开了一种包括双层nFET嵌入式应力元件的半导体结构。 双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。 双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变 。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。 双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。 双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

公开(公告)号：US08378424B2

公开(公告)日：2013-02-19

申请号：US13599573

申请日：2012-08-30

申请人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

发明人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

IPC分类号： H01L29/66

CPC分类号： H01L21/823425 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/823412 ,  H01L22/12 ,  H01L22/34 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.

摘要翻译： 提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。 第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。 第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。 第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。

公开(公告)号：US20120319110A1

公开(公告)日：2012-12-20

申请号：US13599573

申请日：2012-08-30

申请人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

发明人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

IPC分类号： H01L29/36

CPC分类号： H01L21/823425 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/823412 ,  H01L22/12 ,  H01L22/34 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.

摘要翻译： 提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。 第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。 第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。 第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。

公开(公告)号：US08299535B2

公开(公告)日：2012-10-30

申请号：US12823163

申请日：2010-06-25

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

摘要翻译： 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括从底部到顶部的第一外延掺杂半导体材料的第一层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变;第二层 位于第一层顶部的第二外延掺杂半导体材料和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角形单层的上表面上的金属半导体合金触点。

公开(公告)号：US20120261717A1

公开(公告)日：2012-10-18

申请号：US13533499

申请日：2012-06-26

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L27/092

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.

摘要翻译： 公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。 所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。 每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。 至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

公开(公告)号：US20120104507A1

公开(公告)日：2012-05-03

申请号：US12938457

申请日：2010-11-03

申请人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

发明人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823828

摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.

摘要翻译： 一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于 厚度减小 在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。