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公开(公告)号：US11864439B2
公开(公告)日：2024-01-02
申请号：US17621770
申请日：2021-01-19
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
IPC: H10K59/131 , G09G3/3233 , G09G3/3266 , G09G3/3275 , H10K59/121 , H10K102/00
CPC classification number: H10K59/131 , G09G3/3233 , G09G3/3266 , G09G3/3275 , H10K59/121 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2320/0214 , G09G2320/0247 , G09G2330/02 , G09G2330/021 , H10K2102/302
Abstract: Disclosed are a display panel and a display device. The display panel includes a base substrate; a pixel unit on the base substrate and including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit being closer to the base substrate than the light-emitting element and including a driving transistor; a data line configured to provide data signal to the pixel circuit; a connection element through which the light-emitting element is connected with the pixel circuit, the connection element including a shielding portion; and a connection line connected with a gate electrode of the driving transistor. The data line includes two adjacent data lines with the shielding portion located therebetween, and an orthographic projection of the connection line on the base substrate at least partially overlaps with an orthographic projection of the shielding portion on the base substrate.
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公开(公告)号：US11862098B2
公开(公告)日：2024-01-02
申请号：US17628779
申请日：2021-04-09
Applicant: BOE Technology Group Co., Ltd.
Inventor： Guangliang Shang , Jie Zhang , Shuo Huang , Libin Liu , Shiming Shi , Hao Liu , Haoliang Zheng , Xing Yao
IPC: G09G3/3266 , G09G3/36 , G11C19/28
CPC classification number: G09G3/3266 , G09G3/3677 , G11C19/28 , G09G2300/0852 , G09G2310/0286
Abstract: A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.
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Patent Agency Ranking
公开(公告)号：US11798458B2
公开(公告)日：2023-10-24
申请号：US17905620
申请日：2021-08-12
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Guangliang Shang , Jie Zhang , Jiangnan Lu , Mei Li , Libin Liu
IPC: G09G3/3266 , G09G3/20
CPC classification number: G09G3/2092 , G09G2300/0426 , G09G2300/0842 , G09G2310/0267 , G09G2330/021
Abstract: A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit is configured to connect or disconnect the between an input terminal and the first input node under control of a clock signal provided by the clock signal terminal; the charge pump circuit is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal, so that a polarity of the voltage signal of the first input is the same as a polarity of the voltage signal of the first input node, and an absolute value of the voltage value of the voltage signal of the first node is greater than an absolute value of a voltage value of the voltage signal of the first input node.
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公开(公告)号：US11417256B2
公开(公告)日：2022-08-16
申请号：US16474650
申请日：2018-12-28
Inventor： Jie Zhang
Abstract: A shift register unit and a driving method thereof, a gate drive circuit, and a display device are disclosed. The shift register unit includes a first input sub-circuit, a first control sub-circuit, an output sub-circuit, and a second control sub-circuit. The first input sub-circuit is configured to output a first control signal of the first control signal terminal to the first control sub-circuit; the first control sub-circuit is configured to output a second input signal of the second input terminal to the first node, or the first control sub-circuit is configured to output the second input signal to the second control sub-circuit; the second control sub-circuit is configured to output a second clock signal to the second node; or the second control sub-circuit is configured to output a first voltage of the first voltage terminal to the second node under control of a level of the control node.
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35.发明授权公开(公告)号：US10950322B2
公开(公告)日：2021-03-16
申请号：US15752790
申请日：2017-09-04
Inventor： Jun Fan , Jie Zhang , Jiguo Wang , Fuqiang Li
Abstract: A shift register unit circuit is disclosed that includes a first node control circuit, a second node control circuit, and a plurality of output circuits. Each of the plurality of output circuits is connected to a respective output terminal and provides a gate drive signal to the respective output terminal. Also disclosed are a method of driving the shift register unit circuit, a gate drive circuit, and a display apparatus.
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36.发明授权公开(公告)号：US10217428B2
公开(公告)日：2019-02-26
申请号：US15522368
申请日：2015-12-11
Inventor： Jun Fan , Jie Zhang , Fuqiang Li
Abstract: An output control unit of a shift register, a shift register and a driving method thereof, and a gate driving device. The output control unit includes N pull-up units, N pull-down units, and N signal output terminals. The nth pull-up unit is connected with a pull-up node, a high voltage source, an nth clock signal input terminal and an nth pull-down unit, the nth pull-down unit is connected to a pull-down node and a low voltage power source, and a connection point of the nth pull-up unit and the nth pull-down unit is further connected to the nth signal output terminal. The output control unit is configured to: provide clock signals from N clock signal input terminals to the N signal output terminals respectively under the control of a voltage of the pull-up node, and pull down levels of output signals of the N signal output terminals.
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公开(公告)号：US20170038887A1
公开(公告)日：2017-02-09
申请号：US14908648
申请日：2015-08-20
Inventor： Jie Zhang , Jun Fan , Fuqiang Li , Xue Dong , Xiaochuan Chen
IPC: G06F3/041 , G06F3/047 , G02F1/1368 , G02F1/1333 , G02F1/1343 , G06F3/044 , G02F1/1362
CPC classification number: G06F3/0416 , G02F1/1333 , G02F1/133308 , G02F1/133345 , G02F1/13338 , G02F1/134336 , G02F1/13439 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/134318 , G02F2201/121 , G02F2201/123 , G06F3/0412 , G06F3/044 , G06F3/047 , G06F2203/04103
Abstract: An in-cell touch screen and display device, which multiplex the common electrode layer as self-capacitance electrodes using self-capacitance principle, modify the pattern of the common electrode layer to segment it into a plurality of independent self-capacitance electrodes, and add on the array substrate touch control data lines that connect the respective self-capacitance electrodes to the touch control detection chip. Orthographic projections of the respective touch control data lines on the array substrate are all within areas where gaps between the pixel areas reside, so as to not affect the aperture ratio of pixel. Embodiments of the present invention modify the structure of the common electrode layer to segment it into self-capacitance electrodes, thus avoiding additional processes of manufacturing an array substrate, saving the production cost, and improving the production efficiency.
Abstract translation: 使用自电容原理将公共电极层复用为自电容电极的单元内触摸屏和显示装置修改公共电极层的图案，将其分割成多个独立的自电容电极，并添加 在将各个自身电容电极连接到触摸控制检测芯片的阵列基板上的触摸控制数据线。 阵列基板上的各个触摸控制数据线的正交投影都在像素区域之间的间隙位于的区域内，从而不影响像素的开口率。 本发明的实施例改变了公共电极层的结构，将其分割为自电容电极，从而避免了制造阵列基板的额外工艺，节省了生产成本，提高了生产效率。
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