DISPLAY SUBSTRATE CONFIGURED WITH DIFFERENT DRIVE MODES, DRIVING METHOD THEREOF, AND DISPLAY APPARATUS

    公开(公告)号:US20250166568A1

    公开(公告)日:2025-05-22

    申请号:US19032469

    申请日:2025-01-21

    Abstract: Provided is a display substrate, a drive method thereof and a display apparatus, the display substrate includes: a first drive mode and a second drive mode, the first drive mode has a refresh rate less than that of the second drive mode, wherein the contents displayed on the display substrate include a plurality of display frames, in the first drive mode, the display frames include: a refresh frame and at least one maintain frame; the display substrate includes pixel circuits arranged in an array, the pixel circuits include a data signal line and a first initial signal line; the data signal line provides a first data signal in the maintain frame, the voltage value of the first data signal is constant, and/or the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, the first initial signal is an AC signal.

    DISPLAY PANEL, DISPLAY APPARATUS, AND METHOD FOR DRIVING DISPLAY PANEL

    公开(公告)号:US20250124879A1

    公开(公告)日:2025-04-17

    申请号:US18687988

    申请日:2022-11-24

    Abstract: Provided are a display panel, a display apparatus and a method for driving the display panel. The display panel includes: multiple gate lines; and multiple shift register units, a target shift register unit of the shift register units includes: a frame trigger selecting circuit and a gate driving circuit; the frame trigger selecting circuit is coupled to a frame trigger input terminal and frame starting signal terminals corresponding to N cascade groups, and outputs, in response to an nth turn-on signal of N turn-on signals corresponding to an nth cascade group, a starting signal input to the frame trigger input terminal to a frame starting signal terminal corresponding to the nth cascade group; 1≤n≤N, and n is an integer; the nth cascade group scans the gate lines coupled thereto line by line after the frame starting signal terminal corresponding thereto receives the starting signal.

    ARRAY SUBSTRATE AND DISPLAY DEVICE
    38.
    发明公开

    公开(公告)号:US20240177662A1

    公开(公告)日:2024-05-30

    申请号:US17789918

    申请日:2021-06-29

    Abstract: An array substrate and a display device are provided. The array substrate includes a plurality of pixel driving circuits, each of which includes a driving transistor, a first light emitting control transistor, a compensation transistor, a first initialization transistor and a second initialization transistor; a first electrode of the first initialization transistor and a first electrode of the first light emitting control transistor are connected to a first node; a first electrode of the second initialization transistor and a first electrode of the compensation transistor are connected to a second node, a second electrode of the first initialization transistor is configured to receive the first initialization signal, and a cathode of the light emitting element is configured to receive a first driving signal, and a difference between a potential of the first initialization signal and a potential of the first driving signal is less than 1.5V.

    SHIFT REGISTER CIRCUIT AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE

    公开(公告)号:US20240071312A1

    公开(公告)日:2024-02-29

    申请号:US17765045

    申请日:2021-03-23

    CPC classification number: G09G3/3266 G09G2310/0286 G11C19/287

    Abstract: A shift register circuit includes a first control sub-circuit and a first output sub-circuit. The first control sub-circuit is configured to: adjust a voltage of a first node to a turn-on voltage due to an influence of a first direct current voltage signal from a first clock signal terminal, an initial voltage signal from an initial signal terminal and a second direct current voltage signal from a second clock signal terminal; and maintain the voltage of the first node at the turn-on voltage due to an influence of a first clock signal from the first clock signal terminal and a second clock signal from the second clock signal terminal. The first output sub-circuit is configured to be turned on under a control of the turn-on voltage of the first node to transmit a first voltage signal from a first voltage terminal to a signal output terminal.

Patent Agency Ranking