公开(公告)号：US08759947B2

公开(公告)日：2014-06-24

申请号：US13430778

申请日：2012-03-27

申请人： Juan Boon Tan ,  Yeow Kheng Lim ,  Shao Ning Yuan ,  Soh Yun Siah ,  Shunqiang Gong

发明人： Juan Boon Tan ,  Yeow Kheng Lim ,  Shao Ning Yuan ,  Soh Yun Siah ,  Shunqiang Gong

IPC分类号： H01L21/02

CPC分类号： H01L23/5223 ,  H01L23/481 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate.

摘要翻译： 背面MOM / MIM结构集成在具有前端电路的设备上。 实施例包括形成具有与前侧相对的前侧和后侧的基板，所述基板在基板的正面上包括电路; 以及在衬底的背面上形成金属 - 氧化物 - 金属（MOM）电容器，金属 - 绝缘体 - 金属（MIM）电容器或其组合。 其他实施例包括在衬底中形成穿硅通孔（TSV），将MOM电容器，MIM电容器或其组合连接到衬底前侧上的电路。

公开(公告)号：US20130187280A1

公开(公告)日：2013-07-25

申请号：US13357960

申请日：2012-01-25

申请人： Shaoning Yuan ,  Yue Kang Lu ,  Yeow Kheng Lim ,  Juan Boon Tan

发明人： Shaoning Yuan ,  Yue Kang Lu ,  Yeow Kheng Lim ,  Juan Boon Tan

IPC分类号： H01L23/48

CPC分类号： H01L23/585 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/014

摘要： The subject matter disclosed herein relates to structures formed on semiconductor chips that are used for at least partially addressing the thermally induced stresses and metallization system cracking problems in a semiconductor chip that may be caused by the presence of through-silicon vias (TSV's), and which may be due primarily to the significant differences in thermal expansion between the materials of the TSV's and the semiconductor-based materials that generally make up the remainder of the semiconductor chip. One device disclosed herein includes a substrate and a crack-arresting structure positioned above the substrate, the crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above. The device also includes a conductive structure positioned at least partially within the perimeter of the crack-arresting structure, and a conductive element extending through an opening in the crack-arresting structure, wherein the conductive element is conductively coupled to the conductive structure.

摘要翻译： 本文公开的主题涉及形成在半导体芯片上的结构，其用于至少部分地解决半导体芯片中可能由于存在穿硅通孔（TSV）而导致的热诱导应力和金属化系统开裂问题，以及 这可能主要是由于TSV的材料与通常构成半导体芯片的其余部分的半导体材料之间的热膨胀的显着差异。 本文公开的一种装置包括基底和位于基底上方的裂缝阻止结构，所述裂缝阻止结构包括多个裂缝阻止元件，并且当从上方观察时具有周边。 该装置还包括至少部分地位于裂缝阻止结构的周边内的导电结构，以及延伸穿过裂缝阻止结构中的开口的导电元件，其中导电元件与导电结构导电耦合。

公开(公告)号：US06352904B2

公开(公告)日：2002-03-05

申请号：US09726251

申请日：2000-11-30

申请人： Juan Boon Tan ,  Soon Ee Neoh

发明人： Juan Boon Tan ,  Soon Ee Neoh

IPC分类号： H01L23544

CPC分类号： G03F9/708 ,  G03F9/7076 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for generating alignment marks on the scribe lines in which alignment marks are generated only at oxide layers is described. An alignment mark is formed in an oxide layer on a scribe line of a wafer. The alignment mark is lined with a metal layer and filled with a dielectric layer which is planarized. The alignment mark is used in aligning a reticle to pattern the metal layer and is also used in aligning a reticle to pattern the dielectric layer wherein the step of lining the alignment mark with the metal layer protects the alignment mark.

摘要翻译： 描述在仅在氧化物层上产生对准标记的划线上产生对准标记的方法。 在晶片的划线上的氧化物层中形成对准标记。 对准标记衬有金属层，并填充有平坦化的介电层。 对准标记用于对准掩模版以图案化金属层，并且还用于对准掩模版以图案化电介质层，其中将对准标记与金属层衬里的步骤保护对准标记。

公开(公告)号：US06235437B1

公开(公告)日：2001-05-22

申请号：US09458731

申请日：1999-12-13

申请人： Soon Ee Neoh ,  Juan Boon Tan ,  Zadig Cheung-Ching Lam ,  Kay Chai Ang

发明人： Soon Ee Neoh ,  Juan Boon Tan ,  Zadig Cheung-Ching Lam ,  Kay Chai Ang

IPC分类号： G03F900

CPC分类号： G03F9/7076 ,  G03F9/7069 ,  G03F9/7088 ,  Y10S438/975

摘要： A multi-segment alignment mark useful for a variety of processes is described. The multi-segment alignment mark comprises a plurality of segments wherein each of the segments comprises a series of sub-segments wherein each of the sub-segments comprises a series of spaces and lines, each sub-segment having the same width but having a different number of spaces and lines within the width depending on the relative width of the spaces and lines. A wafer stepper detects signals from each of the sub-segments and uses the best signal to achieve alignment.

摘要翻译： 描述了可用于各种过程的多段对准标记。 多段对准标记包括多个段，其中每个段包括一系列子段，其中每个子段包括一系列空间和线，每个子段具有相同的宽度但是具有不同的 宽度内的空格和行数取决于空格和行的相对宽度。 晶片步进器检测来自每个子段的信号，并使用最佳信号来实现对准。

公开(公告)号：US6146969A

公开(公告)日：2000-11-14

申请号：US234092

申请日：1999-01-19

申请人： Juan Boon Tan ,  Soon Ee Neoh ,  Phuan Yee Hwee

发明人： Juan Boon Tan ,  Soon Ee Neoh ,  Phuan Yee Hwee

IPC分类号： H01L23/544 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002

摘要： Scribeline alignment marks and a method of forming the scribeline alignment marks are provided for auxiliary alignment marks on an integrated circuit wafer. The scribeline alignment marks have the same shape and size as the contact holes formed in a layer of dielectric. The scribeline alignment marks are located in alignment rectangles in an X and Y array filling each of the alignment rectangles. Since the alignment marks have the same size and shape as the contact holes the alignment marks will not be overexposed when they are formed using a photolithographic process optimized for the contact holes. When the alignment marks are filled with metal and the wafer is planarized a step height between the top of the metal in the alignment mark hole and the dielectric allows the alignment marks to be used for automatic wafer positioning.

摘要翻译： 为集成电路晶片上的辅助对准标记提供了划线对准标记和形成划线对准标记的方法。 划线对准标记与形成在电介质层中的接触孔具有相同的形状和尺寸。 划线对准标记位于填充每个对齐矩形的X和Y阵列中的对齐矩形中。 由于对准标记具有与接触孔相同的尺寸和形状，因此当使用针对接触孔优化的光刻工艺形成时，对准标记不会被过度曝光。 当对准标记被金属填充并且晶片被平坦化时，对准标记孔中的金属顶部与电介质之间的台阶高度允许对准标记用于自动晶片定位。