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公开(公告)号：US07272029B2
公开(公告)日：2007-09-18
申请号：US11025778
申请日：2004-12-29
IPC分类号： G11C11/00
摘要： A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.
摘要翻译： 读出放大器转换将输出信号编码到总线上，使得当感测到的位线具有与先前感测的位线的状态不同的状态时，总线信号仅转变。 读出放大器包括当总线信号被断言时改变状态的存储元件。 基于存储元件的状态，读出放大器的输出有条件地反转。
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32.发明授权Memory with reduced sub-threshold leakage current in dynamic bit lines of read ports 有权在读端口的动态位线中具有降低的亚阈值泄漏电流的存储器公开(公告)号：US06643199B1
公开(公告)日：2003-11-04
申请号：US10162929
申请日：2002-06-04
申请人： Stephen H. Tang , Steven K. Hsu , Vivek K. De , Shih-Lien L. Lu
发明人： Stephen H. Tang , Steven K. Hsu , Vivek K. De , Shih-Lien L. Lu
IPC分类号： G11C700
CPC分类号： G11C11/412
摘要： For a memory cell, where an access transistor couples the memory cell to a local bit line, a pMOSFET essentially eliminates sub-threshold leakage current in the access transistor when the memory cell is not being read, and when the memory cell is being read, an additional pMOSFET essentially eliminates sub-threshold leakage current in the access transistor if the memory cell stores an information bit such that it does not discharge the local bit line. In this way, a half-keeper connected to the local bit line does not need to contend with sub-threshold leakage current.
摘要翻译： 对于存储晶体管，其中存取晶体管将存储单元耦合到局部位线，当存储单元未被读取时，pMOSFET基本上消除了存取晶体管中的次阈值泄漏电流，并且当存储单元被读取时， 如果存储单元存储信息位，使得其不释放局部位线，附加的pMOSFET基本上消除了存取晶体管中的次阈值漏电流。 以这种方式，连接到本地位线的半保持器不需要与亚阈值泄漏电流相抗衡。
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公开(公告)号：US06628143B2
公开(公告)日：2003-09-30
申请号：US09965360
申请日：2001-09-26
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.
摘要翻译： 全驱动，源极跟随器泄漏容限动态逻辑门的实施例包括nMOSFET逻辑，用于在评估阶段对节点进行有条件充电，并且在预充电阶段期间将节点充电至相对小的电压，使得nMOSFET 逻辑变为反向偏置。
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34.发明授权公开(公告)号：US09059715B2
公开(公告)日：2015-06-16
申请号：US13997584
申请日：2011-11-14
IPC分类号： H03L5/00 , H03K19/0185 , H03K3/356
CPC分类号： H03L5/00 , H03K3/356182 , H03K19/018507
摘要： Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area consumption.
摘要翻译： 通过中压控制争用中断实现电压电平转换的方法和系统。 电压电平移位器（VLS）可以包括电压电平移位电路，用于将输入逻辑状态从输入电压摆幅电平移位到输出电压摆幅。 VLS可以包括争用电路，争用中断器和中断控制器，以产生具有临时电压摆幅的争用中断控制。 临时电压摆幅的下限可以对应于输出电压摆幅的下限。 临时电压摆幅的上限可以对应于输入电压摆幅的上限。 可以实现VLS以实现水平移位真实和互补的逻辑状态，例如用共源共栅电压开关逻辑（CVSL）。 临时电压控制的争用中断器可能有助于在相对较小的延迟和相对较小的功率和面积消耗的情况下，在竞争中断器的基于过程的电压可靠限度内维持电压。
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公开(公告)号：US07800407B1
公开(公告)日：2010-09-21
申请号：US12492938
申请日：2009-06-26
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： To pre-charge a node to one of first and second voltage levels in response to inputs received at the corresponding voltage level, to selectively level shift the node from the first voltage level to the second voltage level when in a first voltage mode, and to maintain the node at the second voltage level when in a second voltage mode. Level shifting from first voltage level may be performed within one gate stage that may be bypassed when in the second voltage mode. The node may be discharged with no delay difference between the first and second voltage modes. Inputs may include a clock signal, which may be received at either of the first and second voltage levels without level shifting the clock signal. A circuit may be implemented with a multi-core processor system to permit selective voltage mode operation of the cores.
摘要翻译： 为了响应于在相应电压电平处接收到的输入，将节点预充电到第一和第二电压电平之一，以便当在第一电压模式下选择性地将节点从第一电压电平移位到第二电压电平，并且 当处于第二电压模式时，将节点保持在第二电压电平。 可以在一个门级内执行从第一电压电平的电平转换，当处于第二电压模式时，可能被旁路。 可以在第一和第二电压模式之间没有延迟差放电节点。 输入可以包括时钟信号，其可以在第一和第二电压电平中的任何一个处接收，而不会对时钟信号进行电平移位。 电路可以用多核处理器系统来实现，以允许芯的选择性电压模式操作。
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36.发明申请Ultra wide voltage range register file circuit using programmable triple stacking 审中-公开超宽电压范围寄存器文件电路采用可编程三重堆叠公开(公告)号：US20090168557A1
公开(公告)日：2009-07-02
申请号：US12006276
申请日：2007-12-31
IPC分类号： G11C5/14
摘要： Methods and apparatus relating to expanding the operational voltage range of data storage circuits are described. In an embodiment, low voltage data storage circuit operation is improved by driving a transistor with a control word line programmable circuit. Other embodiments are also described.
摘要翻译： 描述了扩展数据存储电路的工作电压范围的方法和装置。 在一个实施例中，通过用控制字线可编程电路驱动晶体管来提高低电压数据存储电路操作。 还描述了其它实施例。
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公开(公告)号：US07332937B2
公开(公告)日：2008-02-19
申请号：US11321328
申请日：2005-12-28
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , G01R31/3008 , G01R31/31721 , H03K19/00361 , H03K19/00384
摘要： Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.
摘要翻译： 这里公开了用于向动态逻辑电路提供自适应保持器功能的解决方案。 在一些实施例中，可编程保持器电路耦合到寄存器文件电路。 包括泄漏指示器电路，用于在寄存器文件的至少一部分中建模泄漏。 控制电路耦合到泄漏指示器电路和可编程保持器电路，以根据建模的泄漏来控制保持器强度。 要求保护或以其他方式公开其他实施例。
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公开(公告)号：US06404234B1
公开(公告)日：2002-06-11
申请号：US09851917
申请日：2001-05-09
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A domino logic circuit and method comprise at least two series-connected domino logic stages with each domino logic stage comprising a dynamic stage and a static stage. A variable virtual ground of the first domino logic's static stage is switched to a voltage level below a circuit ground level when a received clock signal and a second domino logic stage's dynamic output are both high, indicating the second domino logic circuit stage is in the evaluation phase.
摘要翻译： 多米诺逻辑电路和方法包括至少两个串联连接的多米诺逻辑级，每个多米诺逻辑级包括动态级和静态级。 当接收到的时钟信号和第二多米诺逻辑级的动态输出均为高电平时，第一多米诺逻辑逻辑静态级的可变虚拟接地切换到低于电路接地电平的电压电平，表明第二多米诺逻辑电路级处于评估状态 相。
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