公开(公告)号：US07422961B2

公开(公告)日：2008-09-09

申请号：US10389456

申请日：2003-03-14

Applicant: Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温工艺可以是CVD工艺。

公开(公告)号：US20080054316A1

公开(公告)日：2008-03-06

申请号：US11926655

申请日：2007-10-29

Applicant: Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L29/78

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US06858503B1

公开(公告)日：2005-02-22

申请号：US10358484

申请日：2003-02-05

Applicant: Minh V. Ngo ,  Ming-Ren Lin ,  Paul R. Besser ,  Qi Xiang ,  Eric N. Paton ,  Jung-Suk Goo

Inventor： Minh V. Ngo ,  Ming-Ren Lin ,  Paul R. Besser ,  Qi Xiang ,  Eric N. Paton ,  Jung-Suk Goo

IPC: H01L21/306 ,  H01L29/10 ,  H01L21/336

CPC classification number: H01L21/02046 ,  H01L29/1054

Abstract: A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabrication lines and strained silicon (SMOS) fabrication lines. The protocol allows better silicidation in SMOS devices.

Abstract translation: 制造系统利用从晶片顶表面去除锗的方案。 暴露于气体，如含有盐酸的气体，可以从上表面除去锗。 该协议可以允许在Flash产品制造线和应变硅（SMOS）生产线中使用共享设备。 该协议允许在SMOS器件中更好的硅化。

公开(公告)号：US06764966B1

公开(公告)日：2004-07-20

申请号：US10085278

申请日：2002-02-27

Applicant: William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

Inventor： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

IPC: H01L2128

CPC classification number: H01L29/6656 ,  H01L29/66833 ,  H01L29/78

Abstract: A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.

Abstract translation: 公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。 半导体器件包括插入在栅电极和半导体衬底之间的电介质层。 此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。 梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

公开(公告)号：US06248675B1

公开(公告)日：2001-06-19

申请号：US09369099

申请日：1999-08-05

Applicant: Qi Xiang ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Ming-Ren Lin

IPC: H01L21302

CPC classification number: H01L21/02672 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/76229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and a crystallization enhancing layer is deposited on the bottom wall of the gate opening. Amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening after the crystallization enhancing layer has been deposited. Dual gates for both an N-channel field effect transistor and a P-channel field effect transistor are formed by doping the amorphous gate electrode material with an N-type dopant for an N-channel field effect transistor, and by doping the amorphous gate electrode material with a P-type dopant for a P-channel field effect transistor. The amorphous gate electrode material in the gate opening is then annealed at a relatively low temperature, such as 500° Celsius, using an enhanced crystallization process to convert the amorphous gate electrode material, such as amorphous silicon, into polycrystalline gate electrode material, such as polycrystalline silicon. Thus, relatively low temperatures are used in the present invention to preserve the integrity of the gate dielectric having the high dielectric constant.

Abstract translation: 一种用于制造具有双栅极和具有高介电常数的栅极电介质的短沟道场效应晶体管的方法。 场效应晶体管最初被制造成具有牺牲栅极电介质和虚拟栅电极。 使用具有牺牲栅极电介质和虚拟栅电极的场效应晶体管，使用相对较高的温度进行任何制造工艺，例如场效应晶体管的源极和漏极的激活退火或腐蚀退火。 从场效应晶体管蚀刻伪栅电极和牺牲栅电介质以形成栅极开口。 在栅极的侧壁和底壁上沉积具有高介电常数的电介质层，并且在栅极开口的底壁上沉积结晶增强层。 沉积结晶增强层之后，沉积非晶态栅极材料，例如非晶硅，以填充栅极开口。 通过用N型掺杂剂掺杂非晶栅电极材料来形成用于N沟道场效应晶体管和P沟道场效应晶体管的双栅极，并且通过掺杂非晶栅电极 具有用于P沟道场效应晶体管的P型掺杂剂的材料。 然后使用增强的结晶工艺在较低温度（例如500℃）下将栅极开口中的非晶栅电极材料退火，以将诸如非晶硅的非晶栅电极材料转化为多晶栅电极材料，例如 多晶硅。 因此，在本发明中使用相对较低的温度来保持具有高介电常数的栅极电介质的完整性。

公开(公告)号：US6165902A

公开(公告)日：2000-12-26

申请号：US187520

申请日：1998-11-06

Applicant: Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

Inventor： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

IPC: H01L21/285 ,  H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/28568

Abstract: Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

Abstract translation: 通过选择性地沉积反应阻挡层并在反应阻挡层上选择性地沉积金属层，在源/漏区和栅电极上形成低电阻触点。 实施方案包括选择性沉积钴和钨的合金，其用作反应阻挡层，防止选择性沉积在其上的镍或钴层的硅化。 实施例还包括定制钴钨合金的组成，使得在其下形成薄的硅化物层以降低接触电阻。

公开(公告)号：US6144063A

公开(公告)日：2000-11-07

申请号：US47951

申请日：1998-03-25

Applicant: Geoffrey Choh-Fei Yeap ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Geoffrey Choh-Fei Yeap ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/72

CPC classification number: H01L21/28229 ,  H01L29/42364 ,  H01L29/6659

Abstract: A semiconductor device having a transistor or capacitor with an ultra-thin oxide, which is thinner than 10 angstrom in thickness, is manufactured by eliminating a gate oxidation step in the processing and using the polysilicon reoxidation step to create the ultra-thin gate oxide by diffusion after formation of the gate.

Abstract translation: 通过在处理中消除栅极氧化步骤并使用多晶硅再氧化步骤来制造具有厚度小于10埃的超薄氧化物的晶体管或电容器的半导体器件，以通过在多晶硅再氧化步骤中产生超薄栅极氧化物 形成门后扩散。

公开(公告)号：US6093594A

公开(公告)日：2000-07-25

申请号：US69879

申请日：1998-04-29

Applicant: Geoffrey Choh-Fei Yeap ,  Qi Xiang ,  Ming-Ren Lin

Inventor： Geoffrey Choh-Fei Yeap ,  Qi Xiang ,  Ming-Ren Lin

IPC: H01L21/8238

CPC classification number: H01L21/823864

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device is processed after the formation of the gates and gate oxides by N-type dopant implantation to form N-type shallow source and drain extension junctions. Spacers are formed for N-type dopant implantation to form N-type deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the NMOS source and drain extension junctions and junctions, and the spacers are removed. A thin oxide spacer is used to displace P-type dopant implantation to P-type shallow source and drain extension junctions. A nitride spacer is then formed for P-type dopant implantation to form P-type deep source and drain junctions. A second lower temperature rapid thermal anneal then independently optimizes the PMOS source and drain junctions independently from the NMOS source and drain junctions.

Abstract translation: 在通过N型掺杂剂注入形成栅极和栅极氧化物之后，处理超大规模CMOS集成电路半导体器件，以形成N型浅源极和漏极延伸结。 形成N型掺杂剂注入以形成N型深源极和漏极结的间隔物。 然后，较高温度的快速热退火优化NMOS源极和漏极延伸接合点和结，并且去除间隔物。 使用薄氧化物间隔物将P型掺杂剂注入位移到P型浅源极和漏极延伸结。 然后形成用于P型掺杂剂注入以形成P型深源极和漏极结的氮化物间隔物。 然后，第二较低温度的快速热退火独立地优化PMOS源极和漏极结，这些独立于NMOS源极和漏极结。

公开(公告)号：US06060364A

公开(公告)日：2000-05-09

申请号：US260880

申请日：1999-03-02

Applicant: Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

Inventor： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78654

Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.

Abstract translation: 形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124） 氧化物（122）。 随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一 区域（60）和在其间具有沟道区（58）的第二区域（68）。 方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域 （60）和第二区域（68）中的源极区域（70）。 源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。 源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。

公开(公告)号：US5960322A

公开(公告)日：1999-09-28

申请号：US994308

申请日：1997-12-19

Applicant: Qi Xiang ,  Geoffrey Yeap ,  Srinath Krishnan ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Geoffrey Yeap ,  Srinath Krishnan ,  Ming-Ren Lin

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L29/6656 ,  Y10S438/917

Abstract: A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.

Abstract translation: 制造超大规模集成电路半导体器件的方法抑制了硼激活快速热退火期间由于偏析到屏幕氧化物中的硼损失。 在用于超浅，源极和漏极延伸结的硼注入之前，使用屏幕氧化物的氮化将氮掺入屏幕氧化物层中。 在硼注入之前，使用第二屏蔽氧化物的第二次氮化用于更深，源极和漏极结。 该方法显着抑制了硼扩散和离开硅衬底的偏析，从而降低了整个源极和漏极结的串联电阻。