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37 条记录 (耗时 0.022 秒)

    Method for fabricating nitride memory cells using a floating gate fabrication process
    32.
    发明授权
    Method for fabricating nitride memory cells using a floating gate fabrication process 有权
    使用浮栅制造工艺制造氮化物存储单元的方法

    公开(公告)号：US06743677B1

    公开(公告)日：2004-06-01

    申请号：US10306529

    申请日：2002-11-27

    申请人： Mark W. Randolph ,  Darlene G. Hamilton ,  Binh Quang Le ,  Wei Zheng

    发明人： Mark W. Randolph ,  Darlene G. Hamilton ,  Binh Quang Le ,  Wei Zheng

    IPC分类号： H01L21336

    CPC分类号： H01L21/28282

    摘要： The present invention is a method for fabricating nitride memory cells using a floating gate fabrication process. In one embodiment of the present invention, the fabrication process of a floating gate memory cell is accessed. The floating gate memory cell fabrication process is then altered to produce an altered floating gate memory cell fabrication process. The altered floating gate memory cell fabrication process is then used to form a nitride memory cell.

    摘要翻译： 本发明是使用浮栅制造工艺制造氮化物存储单元的方法。 在本发明的一个实施例中，访问浮动栅极存储单元的制造过程。 然后改变浮动栅极存储器单元制造工艺以产生改变的浮动栅极存储器单元制造工艺。 然后使用改变的浮动栅极存储单元制造工艺来形成氮化物存储单元。

    Method and apparatus for adjusting on-chip current reference for EEPROM sensing
    34.
    发明授权
    Method and apparatus for adjusting on-chip current reference for EEPROM sensing 有权
    用于调整EEPROM感应的片内电流参考的方法和装置

    公开(公告)号：US06525966B1

    公开(公告)日：2003-02-25

    申请号：US10010985

    申请日：2001-12-05

    申请人： Shane C. Hollmer ,  Joseph G. Pawletko ,  Binh Quang Le

    发明人： Shane C. Hollmer ,  Joseph G. Pawletko ,  Binh Quang Le

    IPC分类号： G11C1606

    CPC分类号： G11C16/26 ,  G11C16/06

    摘要： Method and apparatus for a memory circuit having a sense amplifier circuit having a sensing amplifier connected to read the data content output of a memory cell where the sense amplifier circuit includes a current source transistor having a gate terminal and having a drain terminal connected to a voltage supply and having a source terminal connected to the sensing amplifier, with a selectable source current in order to account for variation from a desired source current due to variations in the designed source current transistor performance parameters.

    摘要翻译： 一种具有读出放大器电路的存储电路的方法和装置，该读出放大器电路具有连接到读出存储单元的数据内容输出的感测放大器，其中读出放大器电路包括具有栅极端子并具有连接到电压的漏极端子的电流源晶体管 提供并具有连接到感测放大器的源极端子，具有可选择的源极电流，以便考虑到由于设计的源极电流晶体管性能参数的变化而导致的期望源极电流的变化。

    Circuit for fast and accurate memory read operations
    35.
    发明授权
    Circuit for fast and accurate memory read operations 有权
    电路用于快速准确的内存读取操作

    公开(公告)号：US06744674B1

    公开(公告)日：2004-06-01

    申请号：US10387617

    申请日：2003-03-13

    申请人： Binh Quang Le ,  Pauling Chen ,  Roger Tsao

    发明人： Binh Quang Le ,  Pauling Chen ,  Roger Tsao

    IPC分类号： G11C1624

    CPC分类号： G11C16/26 ,  G09G3/2932 ,  G09G2310/06 ,  G09G2310/066 ,  G09G2320/041 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/24

    摘要： A memory circuit senses current in a target cell during a read operation. According to one exemplary embodiment, the memory circuit comprises the target cell, a first neighboring cell, and an operational amplifier. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a drain voltage. A sensing circuit is coupled at a first node to at least one of the first bit line or the second bit line. The first neighboring cell has a third bit line connected to a second node. The operational amplifier has an output terminal connected at the second node to the third bit line. The operational amplifier has a noninverting input terminal connected to said first node, and also has an inverting input terminal connected to the second node.

    摘要翻译： 存储电路在读取操作期间感测目标单元中的电流。 根据一个示例性实施例，存储器电路包括目标单元，第一相邻单元和运算放大器。 第一目标单元具有连接到地的第一位线; 目标单元还具有连接到漏极电压的第二位线。 感测电路在第一节点处耦合到第一位线或第二位线中的至少一个。 第一相邻小区具有连接到第二节点的第三位线。 运算放大器具有在第二节点处连接到第三位线的输出端子。 运算放大器具有连接到所述第一节点的同相输入端子，并且还具有连接到第二节点的反相输入端子。

    Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
    36.
    发明授权
    Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device 有权
    降低栅极氧化物和跨越可擦除存储器件的高电压晶体管内的结的电压应力

    公开(公告)号：US06275424B1

    公开(公告)日：2001-08-14

    申请号：US09774509

    申请日：2001-01-31

    申请人： Binh Quang Le ,  Pauling Chen

    发明人： Binh Quang Le ,  Pauling Chen

    IPC分类号： G11C700

    CPC分类号： G11C16/16 ,  H01L27/115

    摘要： The present invention reduces the voltage across the gate oxide and across a junction of a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) within an unselected block of an electrically erasable memory during an erase operation of a selected block of the electrically erasable memory. The drain node is coupled to each respective control gate node of a plurality of core cells disposed within a well. The present invention includes a voltage generator coupled to a gate node of the high voltage transistor and to the well having the core cells disposed therein. The present invention also includes a microcontroller that controls the voltage generator to ramp up a magnitude of a well voltage applied at the well from a start ramping time when the well voltage is at a start voltage to an end ramping time when the well voltage is at an end voltage. The mictocontroller also controls the voltage generator to couple the drain node of the high voltage MOSFET to a ground node having a ground voltage for a predetermined time period after the start ramping time. The well voltage reaches an intermediate voltage at the predetermined time period after the start ramping time. The microcontroller further controls the voltage generator to uncouple the drain node of the high voltage MOSFET from the ground node at the predetermined time period after the start ramping time. In this manner, the drain node of the high voltage MOSFET has a controlled voltage, with a magnitude that is substantially equal to a magnitude of the end voltage minus a magnitude of the intermediate voltage, at the end ramping time when the well voltage is at the end voltage.

    摘要翻译： 本发明在电可擦除存储器的选定块的擦除操作期间降低栅电氧化物两端的电压，并跨越电可擦除存储器的未选择块内的高电压MOSFET（金属氧化物半导体场效应晶体管）的结。 漏极节点耦合到设置在阱内的多个核心单元的每个相应的控制栅极节点。 本发明包括耦合到高压晶体管的栅极节点的电压发生器和其中设置有核心单元的阱。 本发明还包括一个微控制器，其控制电压发生器，当井电压处于起始电压时，当井电压处于起始电压时到达结束斜坡时间时，从起始斜坡时间斜坡上升施加在井处的阱电压的幅度 结束电压。 微控制器还控制电压发生器，以在开始斜坡时间之后的预定时间段内将高压MOSFET的漏极节点耦合到具有接地电压的接地节点。 在开始斜坡时间之后的预定时间段，阱电压达到中间电压。 微控制器进一步控制电压发生器在开始斜坡时间之后的预定时间段从接地节点将高压MOSFET的漏极节点断开。 以这种方式，高压MOSFET的漏极节点具有受控电压，其幅度基本上等于终端电压的幅度减去中间电压的幅度，当阱电压在 结束电压。

    Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
    37.
    发明授权
    Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device 有权
    降低栅极氧化物和跨越可擦除存储器件的高电压晶体管内的结的电压应力

    公开(公告)号：US06240017B1

    公开(公告)日：2001-05-29

    申请号：US09353267

    申请日：1999-07-14

    申请人： Binh Quang Le ,  Pauling Chen

    发明人： Binh Quang Le ,  Pauling Chen

    IPC分类号： G11C1604

    CPC分类号： G11C16/16 ,  H01L27/115

    摘要： The present invention reduces the voltage across the gate oxide and across a junction of a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) within an unselected block of an electrically erasable memory during an erase operation of a selected block of the electrically erasable memory. The drain node is coupled to each respective control gate node of a plurality of core cells disposed within a well. The present invention includes a voltage generator coupled to a gate node of the high voltage transistor and to the well having the core cells disposed therein. The present invention also includes a microcontroller that controls the voltage generator to ramp up a magnitude of a well voltage applied at the well from a start ramping time when the well voltage is at a start voltage to an end ramping time when the well voltage is at an end voltage. The microcontroller also controls the voltage generator to couple the drain node of the high voltage MOSFET to a ground node having a ground voltage for a predetermined time period after the start ramping time. The well voltage reaches an intermediate voltage at the predetermined time period after the start ramping time. The microcontroller further controls the voltage generator to uncouple the drain node of the high voltage MOSFET from the ground node at the predetermined time period after the start ramping time. In this manner, the drain node of the high voltage MOSFET has a controlled voltage, with a magnitude that is substantially equal to a magnitude of the end voltage minus a magnitude of the intermediate voltage, at the end ramping time when the well voltage is at the end voltage.

    摘要翻译： 本发明在电可擦除存储器的选定块的擦除操作期间降低栅电氧化物两端的电压，并跨越电可擦除存储器的未选择块内的高电压MOSFET（金属氧化物半导体场效应晶体管）的结。 漏极节点耦合到设置在阱内的多个核心单元的每个相应的控制栅极节点。 本发明包括耦合到高压晶体管的栅极节点的电压发生器和其中设置有核心单元的阱。 本发明还包括一个微控制器，其控制电压发生器，当井电压处于起始电压时，当井电压处于起始电压时到达结束斜坡时间时，从起始斜坡时间斜坡上升施加在井处的阱电压的幅度 结束电压。 微控制器还控制电压发生器将高压MOSFET的漏极节点连接到具有接地电压的接地节点，该接地节点在启动斜坡时间之后的预定时间段内。 在开始斜坡时间之后的预定时间段，阱电压达到中间电压。 微控制器进一步控制电压发生器在开始斜坡时间之后的预定时间段从接地节点将高压MOSFET的漏极节点断开。 以这种方式，高压MOSFET的漏极节点具有受控电压，其幅度基本上等于终端电压的幅度减去中间电压的幅度，当阱电压在 结束电压。