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    Apparatus and method for operating chips synchronously at speeds exceeding the bus speed
    34.
    发明授权
    Apparatus and method for operating chips synchronously at speeds exceeding the bus speed 失效
    以超过总线速度的速度同步运行芯片的装置和方法

    公开(公告)号：US5708801A

    公开(公告)日：1998-01-13

    申请号：US744387

    申请日：1996-11-07

    申请人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

    发明人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

    IPC分类号： G06F1/06 ,  G06F13/42 ,  G06F1/12

    CPC分类号： G06F1/06 ,  G06F13/4217

    摘要： A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.

    摘要翻译： 一种数据通信系统，用于在以第一时钟频率运行的总线与在第二时钟频率与数据总线同步工作的电路块之间传送数据。 该系统包括用于产生第一时钟频率的总线时钟信号和第二时钟频率的芯片时钟信号的时钟发生器，其中第一和第二时钟信号频率的比率为（N-1）：N，其中N是 大于1的整数，并且其中总线和芯片时钟信号每芯片时钟信号的N个周期被同步一次。 时钟发生器还产生指示芯片时钟信号周期的同步信号，其中总线和芯片时钟信号同步。 电路块包括用于在总线上接收和发送数据的接口电路。 该系统还包括连接到每个电路块的电路，用于识别芯片时钟信号周期，其中数据不能由总线上的电路块发送，并且芯片时钟信号周期中，电路块不能从总线接收数据， 在N个芯片时钟周期的每个相邻块中存在每种类型的周期中的一种。

    Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
    35.
    发明授权
    Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus 失效
    通过按照在总线上发出的事务的顺序检查一致性来维持高速缓存一致性的多处理器系统

    公开(公告)号：US5530933A

    公开(公告)日：1996-06-25

    申请号：US201463

    申请日：1994-02-24

    申请人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

    发明人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

    IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/06

    CPC分类号： G06F12/0831

    摘要： A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.

    摘要翻译： 与具有总线的系统一起使用的一致性方案，主存储器，用于响应于在总线上接收到的事务来访问主存储器的主存储器控制器，以及耦合到总线的一组处理器模块。 每个处理器模块具有高速缓冲存储器，并且能够将总线上的相干事务发送到其他处理器模块和主存储器控制器。 每个处理器模块检测总线上发出的相干事务，并执行每个相干事务的高速缓存一致性检查。 每个处理器模块具有用于存储在总线上发布的所有事务的一致性队列，并且用于以先入先出顺序执行事务的一致性检查。 当模块在总线上传输一致的事务时，它将自己的事务置于自己的一致性队列中。

    Mat or rug cleaning process using roller brush
    36.
    发明授权
    Mat or rug cleaning process using roller brush 失效
    垫子或地毯清洁过程使用滚刷

    公开(公告)号：US4226641A

    公开(公告)日：1980-10-07

    申请号：US879042

    申请日：1978-02-21

    申请人： Howard E. Bode, Sr. ,  James B. Williams

    发明人： Howard E. Bode, Sr. ,  James B. Williams

    IPC分类号： D06G1/00 ,  B08B1/02 ,  B08B1/04

    CPC分类号： D06G1/00

    摘要： A rug or mat cleaning system is disclosed which is comprised of first a dry lint and dust removing section, then a water or like liquid containing vessel having an initial wash section and then a rinse section and then finally a wringer section. A mat to be cleaned is passed through a first conveying roller at a slower driving speed. Thereafter, the mat or rug enters an increased speed brush which both removes dirt and agitates the surface of the rug and beats it to knock loose undesireable dirt and like particles. In the wash section of the system, alternating feed rollers and brush rollers carry the mat or rug to be cleaned. Each feed roller clamps and holds the rug to prevent slipping while conveying it at a slower linear speed. Each brush roller provides a brushing surface having a substantially higher linear speed than the surface of the conveying rolls. Thus, a "tuck" or crease is created in the rug between each high speed roller brush and its adjacent and following slower conveying roll. A wringer is provided at the end of the system to remove extraneous water from the rug after its cleansing. Pressure belts are provided above the cleaning brushes for enhanced cleaning and operation. A special beater roller with projecting ridges is also included.

    摘要翻译： 公开了一种地毯或垫子清洁系统，其首先包括干燥的棉绒和除尘部分，然后包括具有初始洗涤部分，然后是冲洗部分，然后最后是绞合器部分的含水容器的容器。 要清洁的垫子以较慢的驱动速度通过第一输送辊。 此后，垫子或地毯进入增加速度的刷子，它们都去除污垢并搅动地毯的表面，并打击它以敲入不想要的污垢和类似的颗粒。 在系统的洗涤部分，交替的进料辊和刷辊携带要清洁的垫子或毯子。 每个进给辊夹紧并保持地毯，以防止在以较慢的线速度输送时滑动。 每个刷辊提供具有比输送辊的表面大得多的线速度的刷洗表面。 因此，在每个高速辊刷及其相邻和随后较慢的输送辊之间的地毯中产生“褶皱”或褶皱。 系统末端设有螺旋桨，清洁后从地毯中除去多余的水分。 在清洁刷上方设有压力带，用于增强清洁和操作。 还包括一个特殊的带有凸脊的打浆辊。

    Accelerated sockets
    37.
    发明授权
    Accelerated sockets 有权
    加速插座

    公开(公告)号：US08862682B2

    公开(公告)日：2014-10-14

    申请号：US12707594

    申请日：2010-02-17

    申请人： James B. Williams

    发明人： James B. Williams

    IPC分类号： G06F15/16 ,  H04L29/06

    CPC分类号： H04L69/162 ,  H04L67/1097

    摘要： An improved method of using sockets in connection with TCP over certain local networks, such as the enhanced Ethernet. In particular, an accelerated socket protocol is provided to enhance data communications between different host computer systems connected to an enhanced Ethernet network. Under the accelerated socket protocol, a host computer, while sending a number of data packets, is able to indicate a particular data packet is a last ready data packet out of all packets ready to be sent by setting a PUSH bit in that particular data packet, which triggers an automatic acknowledgement message that confirms receipt of data from the receiver. In addition, while receiving data packets, the host computer can advertise an effective window that corresponds to the actually available receiving space in the host computer.

    摘要翻译： 在某些本地网络（如增强型以太网）上使用与TCP连接的套接字的改进方法。 特别地，提供加速套接字协议以增强连接到增强型以太网的不同主机计算机系统之间的数据通信。 在加速套接字协议下，主计算机在发送多个数据包的同时，能够通过在该特定数据包中设置一个PUSH位来指示特定数据包是准备发送的所有数据包中的最后一个准备好的数据包 ，其触发确认从接收器接收数据的自动确认消息。 此外，在接收数据分组的同时，主计算机可以发布对应于主计算机中实际可用的接收空间的有效窗口。

    Fibre channel over Ethernet
    38.
    发明授权
    Fibre channel over Ethernet 有权
    以太网光纤通道

    公开(公告)号：US08774215B2

    公开(公告)日：2014-07-08

    申请号：US11514665

    申请日：2006-09-01

    申请人： James B. Williams

    发明人： James B. Williams

    IPC分类号： H04L12/50

    CPC分类号： H04L29/06068 ,  H04L12/4633 ,  H04L29/12028 ,  H04L29/12886 ,  H04L61/103 ,  H04L61/6045 ,  H04L69/22

    摘要： The use of Ethernet as an underlying transport for Fiber Channel (FC) frames is disclosed in the Fiber Channel Over Ethernet (FCOE) protocol. In FCOE, the FC physical layer and part of the FC-2 link layer are replaced with the Ethernet physical and link layers. Each FC frame is encapsulated within an Ethernet Frame. The payload of the FCOE frame contains type information from the FC Start Of Frame (SOF) indicator, the FC header, an optional FC payload, and type information from the FC End Of Frame (EOF) indicator. In one embodiment, an Ethernet network carrying FCOE replaces a standard FC network. In another embodiment, devices implementing FCOE may be implemented in a blade server. The entire backplane is Ethernet, over which both storage and networking traffic can be run. The Ethernet links are connected to an Ethernet switch, a FCOE/FC converter, and a FC switch.

    摘要翻译： 在以太网光纤通道（FCOE）协议中公布了以太网作为光纤​​通道（FC）帧的底层传输的使用。 在FCOE中，FC物理层和FC-2链路层的一部分被以太网物理层和链路层替代。 每个FC帧封装在以太网帧中。 FCOE帧的有效载荷包含来自FC起始帧（SOF）指示符，FC头，可选FC有效载荷和FC帧结束（EOF）指示符的类型信息的类型信息。 在一个实施例中，携带FCOE的以太网网络替代标准FC网络。 在另一个实施例中，实现FCOE的设备可以在刀片服务器中实现。 整个背板是以太网，可以运行存储和网络流量。 以太网链路连接到以太网交换机，FCOE / FC转换器和FC交换机。

    Fibre channel over ethernet
    39.
    发明申请
    Fibre channel over ethernet 有权
    以太网上的光纤通道

    公开(公告)号：US20080056300A1

    公开(公告)日：2008-03-06

    申请号：US11514665

    申请日：2006-09-01

    申请人： James B. Williams

    发明人： James B. Williams

    IPC分类号： H04J3/16

    CPC分类号： H04L29/06068 ,  H04L12/4633 ,  H04L29/12028 ,  H04L29/12886 ,  H04L61/103 ,  H04L61/6045 ,  H04L69/22

    摘要： The use of Ethernet as an underlying transport for Fibre Channel (FC) frames is disclosed in the Fibre Channel Over Ethernet (FCOE) protocol. In FCOE, the FC physical layer and part of the FC-2 link layer are replaced with the Ethernet physical and link layers. Each FC frame is encapsulated within an Ethernet Frame. The payload of the FCOE frame contains type information from the FC Start Of Frame (SOF) indicator, the FC header, an optional FC payload, and type information from the FC End Of Frame (EOF) indicator. In one embodiment, an Ethernet network carrying FCOE replaces a standard FC network. In another embodiment, devices implementing FCOE may be implemented in a blade server. The entire backplane is Ethernet, over which both storage and networking traffic can be run. The Ethernet links are connected to an Ethernet switch, a FCOE/FC converter, and a FC switch.

    摘要翻译： 在以太网光纤通道（FCOE）协议中公布了以太网作为光纤​​通道（FC）帧的底层传输的使用。 在FCOE中，FC物理层和FC-2链路层的一部分被以太网物理层和链路层替代。 每个FC帧封装在以太网帧中。 FCOE帧的有效载荷包含来自FC起始帧（SOF）指示符，FC头，可选FC有效载荷和FC帧结束（EOF）指示符的类型信息的类型信息。 在一个实施例中，携带FCOE的以太网网络替代标准FC网络。 在另一个实施例中，实现FCOE的设备可以在刀片服务器中实现。 整个背板是以太网，可以运行存储和网络流量。 以太网链路连接到以太网交换机，FCOE / FC转换器和FC交换机。