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公开(公告)号：US10482827B2
公开(公告)日：2019-11-19
申请号：US15533761
申请日：2016-12-19
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Seungwoo Han , Guangliang Shang
Abstract: The present application discloses a method for driving a display panel, including receiving one or more frames of image data one after another each of which having image data for a plurality of subpixels in the display panel; determining an initial driving voltage corresponding to one subpixel of the plurality of subpixels based on each frame of image data; determining an overdrive voltage corresponding to the one subpixel based on the initial driving voltage and a compensation voltage corresponding to the one subpixel, wherein an amplitude of the overdrive voltage is greater than an amplitude of the initial driving voltage; and applying the overdrive voltage to the one subpixel for an overdrive time period followed by applying the initial driving voltage to a same one subpixel for displaying a subpixel image associated with each frame of image data.
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32.发明申请公开(公告)号：US20190139475A1
公开(公告)日：2019-05-09
申请号：US16126032
申请日：2018-09-10
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zhichong Wang , Haoliang Zheng , Seungwoo Han , Guangliang Shang , Mingfu Han , Lijun Yuan , Xing Yao
Abstract: A shift register circuit, a driving method thereof, a gate drive circuit and a display device are provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a discharge sub-circuit and a noise reduction sub-circuit. The input sub-circuit is connected to an input signal terminal, a first power source terminal and a pull-down node, and configured to, under the control of an input signal, output a first power source terminal signal to the pull-down node. In the shift register circuit, the discharge sub-circuit may control the potential of the pull-down node to be an ineffective potential at the input stage, thereby preventing the noise reduction sub-circuit from affecting the potentials of the pull-up node and the output terminal under the control of the pull-down node, and ensuring normal output of the shift register circuit.
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公开(公告)号：US10255985B2
公开(公告)日：2019-04-09
申请号：US15503830
申请日：2016-08-25
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Mingfu Han , Guangliang Shang , Yuanbo Zhang , Yujie Gao , Yan Yan , Yingmeng Miao , Seungwoo Han , Zhihe Jin , Xing Yao , Haoliang Zheng
Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.
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公开(公告)号：US10210835B2
公开(公告)日：2019-02-19
申请号：US15656419
申请日：2017-07-21
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Mingfu Han , Guangliang Shang , Seungwoo Han , Zhihe Jin , Xing Yao , Haoliang Zheng , Lijun Yuan , Zhichong Wang
Abstract: The present invention discloses a gate driver on array circuit and a driving method thereof, and a display device. The gate driver on array circuit comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to drive in a first working state which is a state in which no defect occurs in the first gate driver on array sub-circuit; the second gate driver on array sub-circuit is configured to drive in a second working state which is a state in which a defect occurs in the first gate driver on array sub-circuit. The present invention improves the yield rate of the gate driver on array circuit.
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公开(公告)号：US12213354B2
公开(公告)日：2025-01-28
申请号：US17585026
申请日：2022-01-26
Applicant: BOE Technology Group Co., Ltd.
Inventor： Hao Chen , Jinxiang Xue , Liang Chen , Jiao Zhao , Li Xiao , Dongni Liu , Seungwoo Han , Haoliang Zheng , Minghua Xuan
IPC: H10K59/131 , G09F9/30 , H10K50/844 , H10K59/121 , H10K102/00
Abstract: A display panel is provided. The display panel includes a base substrate and a plurality of display units disposed on the base substrate. The display unit includes a signal line, a light-emitting device and a drive unit. The light-emitting device is disposed in a flexible display region of the base substrate, the drive unit is disposed in a pixel circuit region of the base substrate, and the signal line is connected with the light-emitting device and the drive unit.
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Patent Agency Ranking
公开(公告)号：US12198608B2
公开(公告)日：2025-01-14
申请号：US18005373
申请日：2021-11-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Li Xiao , Seungwoo Han , Dongni Liu , Haoliang Zheng , Minghua Xuan , Jiao Zhao , Liang Chen , Xiaorong Cui
IPC: G09G3/32
Abstract: A display substrate includes a plurality of data lines extending in a first direction, and a plurality of sub-pixels. A sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a current control circuit, and a duration control circuit electrically connected to the current control circuit and the light-emitting device. The current control circuit is configured to generate a driving signal to drive the light-emitting device to emit light; and the duration control circuit is configured to generate a duration control signal to control a duration of a connection between the current control circuit and the light-emitting device. The current control circuit and the duration control circuit are electrically connected to a same data line.
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37.发明授权公开(公告)号：US12125428B2
公开(公告)日：2024-10-22
申请号：US17923690
申请日：2021-11-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Seungwoo Han , Haoliang Zheng , Dongni Liu , Li Xiao , Jiao Zhao , Xiaorong Cui , Minghua Xuan
CPC classification number: G09G3/32 , G11C19/28 , G09G2300/0842 , G09G2300/0861 , G09G2310/0286 , G09G2310/08
Abstract: A shift register includes: an input circuit configured to receive an input signal; a first control circuit configured to control, in response to a second clock signal and a voltage at a second node, a voltage at the first node; a second control circuit configured to control, in response to a first clock signal, the second clock signal, and the voltage at the first node, a voltage at the second node, and control, in response to the second clock signal and the voltage at the first node, a voltage at the fifth node; and an output circuit configured to transmit, in response to an active level at the first node, a second power signal to an output signal terminal, and transmit, in response to an active level at the fifth node, the first power signal to the output signal terminal. All transistors included in the shift register are N-type transistors.
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公开(公告)号：US12112707B2
公开(公告)日：2024-10-08
申请号：US18308385
申请日：2023-04-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Li Xiao , Haoliang Zheng , Hao Chen , Minghua Xuan , Dongni Liu , Seungwoo Han , Liang Chen , Jiao Zhao , Xue Dong
IPC: G09G3/3258 , G09G3/3291
CPC classification number: G09G3/3258 , G09G3/3291
Abstract: A pixel circuit includes a driving circuit, a first control circuit and a second control circuit. The driving circuit is configured to receive a data signal in response to a scan signal, and generate, in response to a first enable signal, a driving signal according to a first voltage and the data signal. The first control circuit is configured to: receive a first input signal in response to a first control signal, and transmit a third input signal in response to the first input signal; and receive a second input signal in response to a second control signal, and transmit a second enable signal in response to the second input signal. The second control circuit is configured to transmit the driving signal to an element to be driven in response to one of the third input signal and the second enable signal.
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公开(公告)号：US11568777B2
公开(公告)日：2023-01-31
申请号：US17327056
申请日：2021-05-21
Applicant: BOE Technology Group Co., Ltd.
Inventor： Haoliang Zheng , Seungwoo Han , Yi Ouyang , Minghua Xuan
Abstract: The present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit and a driving method thereof, and a display device. The shift register unit includes: a first shift register, a second shift register and a switch control circuit, signal input terminals of the first and second shift registers are coupled to a cascade signal input terminal through the switch control circuit, the switch control circuit is configured to allow a current between the signal input terminal of the first shift register and the cascade signal input terminal or not, and allow a current between the signal input terminal of the second shift register and the cascade signal input terminal or not; the first shift register and the second shift register are configured such that at least one of them operates upon receiving a cascade signal provided by the cascade signal input terminal.
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公开(公告)号：US11328642B2
公开(公告)日：2022-05-10
申请号：US17044148
申请日：2020-03-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Guangliang Shang , Lijun Yuan , Haoliang Zheng , Libin Liu , Xing Yao , Seungwoo Han
IPC: G09G3/20
Abstract: The present disclosure provides a gate driving unit, a gate driving method, a gate driving circuitry and a display device. The gate driving unit includes a reverse-phase gate driving signal output end, a normal-phase gate driving signal output end, an input circuitry, an output control circuitry, an input node control circuitry and an output circuitry. The input circuitry is configured to control an input end to be electrically connected to an input node under the control of a first clock signal. The output control circuitry is configured to control a potential at an output node under the control of a potential at the input node and a second clock signal. The input node control circuitry is configured to control the potential at the input node in accordance with the potential at the output node under the control of the second clock signal. The output circuitry is configured to output a reverse-phase gate driving signal and output a normal-phase gate driving signal in accordance with the potential at the output node.
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