公开(公告)号：US10860763B1

公开(公告)日：2020-12-08

申请号：US14863788

申请日：2015-09-24

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Yuhei Hayashi

IPC: G06F30/331 ,  G06F9/455

Abstract: Disclosed herein are systems and methods of compiling resources of a programmable emulation system to execute an emulation process, to emulate a logic system, such as an application-specific integrated circuit (ASIC), currently being tested and prototyped, and then revising, transforming, and moving the compiled instructions sets to inexpensively, quickly, and dynamically adapt to unavailable resources, which may be due to previously allocation to a different emulation job, or for fault tolerance. Relocation of the resources that will execute the emulation job (i.e., “footprint”) may refer to the remapping of a compiled footprint to a revised set of resources, defining a revised footprint. Fault tolerance may refer to support for working around faulty hardware components of the emulation system.

公开(公告)号：US10536553B1

公开(公告)日：2020-01-14

申请号：US14846460

申请日：2015-09-04

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Sharon Mutchnik ,  Hitesh Gannu ,  Ramesh Mogili

IPC: G06F13/00 ,  H04L29/08

Abstract: An emulation system comprises an outband traffic generating device comprising at least one field programmable gate array coupled to a host system. The outband traffic generating device is configured to transfer one or more bits via an outband channel to a register of an inband traffic generating device. The inband traffic generating device comprises at least one field programmable gate array coupled to a target system. The inband traffic generating device is configured to transfer the one or more bits via an inband channel to the outband traffic generating device.

公开(公告)号：US10303230B1

公开(公告)日：2019-05-28

申请号：US15339279

申请日：2016-10-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Yuhei Hayashi ,  Beshara Elmufdi ,  Hitesh Gannu

IPC: G06F1/00 ,  G06F1/26 ,  G06F9/48 ,  G06F9/30

Abstract: Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions responsive to compiling a netlist file. The method further includes storing, by the compiling processor, a set of execution instructions into an instruction memory of an execution processor. The method further includes generating, by a compiling processor, a set of one or more keephot instructions for the execution processor based upon the set of execution instructions stored into the instruction memory of the execution processor. The method further includes storing, by a compiling processor, the set of keephot instructions into the instruction memory of the execution processor.

公开(公告)号：US10198538B1

公开(公告)日：2019-02-05

申请号：US14981270

申请日：2015-12-28

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Barton Quayle ,  Mitchell G. Poplack ,  Sundar Rajan ,  Chuck Berghorn

IPC: G06F17/50 ,  G06F15/173 ,  H03M1/66

Abstract: The embodiments described herein may improve utilization of an emulator system's resources, and may improve efficiency and effectiveness in bug-identification and/or target-debugging; the components described herein may improve utilization of the emulator's resources, reduce wait time to execute emulation routines, and may limit or eliminate the need to stop or kill emulations in process. The various embodiments described herein allow for dynamically associating domains and targets by dynamically allocating and assigning domains with particular target connections, which are pins and/or wires that connect target pods to the emulation system. An emulation system may comprise one or more target MUXs that are situated between the target connections and the domains, to allow the relationships between target pods and domains to be identified and switched dynamically. The target MUXs may be reprogrammed while emulations are ongoing, in order to redirect data communications between available domains and target pods of target systems.

公开(公告)号：US09379846B1

公开(公告)日：2016-06-28

申请号：US14578173

申请日：2014-12-19

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell G. Poplack ,  Simon Sabato

IPC: H03M13/00 ,  H04L1/00 ,  G06F11/10

CPC classification number: H04L1/0041 ,  G06F11/10 ,  H04L1/0071

Abstract: In one form a method of encoding a data word for serial transmission is provided, where a data word comprising a plurality of data bits is received, an invert bit having a bit value is appended to the data word, the data bits and invert bit are scrambled, ECC check bits are generated, and the data bits, invert bit, and ECC check bits are shuffled together to form an encoded word to be transmitted from a transmitter. A receiver may decode by implementing a decode process with error correction. The encoded word may also be DC balanced by checking the disparity of the bits to be encoded against a running disparity to invert or not the bits. An integrated circuit serializer/deserializer comprises hardware to perform encoding and/or decoding. A hardware functional verification system may implement the disclosed encoding/decoding for interconnections between emulation chips.

Abstract translation: 提供一种编码用于串行传输的数据字的方法，其中接收包括多个数据位的数据字，将具有位值的反转比特附加到数据字，数据位和反转位是 生成ECC校验位，并将数据位，反转位和ECC校验位混合在一起形成要从发送器发送的编码字。 接收机可以通过实施具有纠错的解码过程进行解码。 编码的字也可以通过根据运行的差异检查待编码的比特的差异来反转或不转换比特来进行直流平衡。 集成电路串行器/解串器包括执行编码和/或解码的硬件。 硬件功能验证系统可以实现所公开的编码/解码以用于仿真芯片之间的互连。