中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.017 seconds)

    Dynamic one-bit multiplexing switch for emulation interconnect
    2.
    发明授权
    Dynamic one-bit multiplexing switch for emulation interconnect 有权

    公开(公告)号：US11275598B1

    公开(公告)日：2022-03-15

    申请号：US16208447

    申请日：2018-12-03

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Mitchell G. Poplack ,  Yuhei Hayashi

    IPC: G06F9/455 ,  H04L49/101 ,  H04L45/00 ,  G06F13/10 ,  G06F13/38

    Abstract: The embodiments disclosed herein describe a switching ASIC that provides a dynamic single-bit routing and multiplexing function in an emulation system. The switching ASIC may receive a set of incoming data streams from a first set of emulation devices (e.g., emulation ASICs), disassemble each data stream to the constituent bits, dynamically multiplex the bits, reassemble the multiplexed bits into outgoing data streams, and transmit the outgoing data streams to a second set of emulation devices. Multiple statically scheduled selection tables (UCSWs), one for each output lane of the switching ASIC, drive the selection and routing of bits from input slots of various input lanes to the output slots of the output lane.

    Emulation system supporting representation of four-state signals
    3.
    发明授权
    Emulation system supporting representation of four-state signals 有权

    公开(公告)号：US11900135B1

    公开(公告)日：2024-02-13

    申请号：US16212363

    申请日：2018-12-06

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Mitchell G Poplack ,  Yuhei Hayashi

    IPC: G06F3/00 ,  G06F9/455

    CPC classification number: G06F9/45504

    Abstract: An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.

    Architecture and methodology for tuning clock phases to minimize latency in a serial interface
    4.
    发明授权
    Architecture and methodology for tuning clock phases to minimize latency in a serial interface 有权

    公开(公告)号：US11467620B1

    公开(公告)日：2022-10-11

    申请号：US16217503

    申请日：2018-12-12

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Yuhei Hayashi ,  Mitchell G. Poplack

    IPC: G06F1/08 ,  G06F13/42 ,  G06N20/00 ,  G06F13/40

    Abstract: Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.

    Data routing and multiplexing architecture to support serial links and advanced relocation of emulation models
    6.
    发明授权
    Data routing and multiplexing architecture to support serial links and advanced relocation of emulation models 有权

    公开(公告)号：US10860763B1

    公开(公告)日：2020-12-08

    申请号：US14863788

    申请日：2015-09-24

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Mitchell G. Poplack ,  Yuhei Hayashi

    IPC: G06F30/331 ,  G06F9/455

    Abstract: Disclosed herein are systems and methods of compiling resources of a programmable emulation system to execute an emulation process, to emulate a logic system, such as an application-specific integrated circuit (ASIC), currently being tested and prototyped, and then revising, transforming, and moving the compiled instructions sets to inexpensively, quickly, and dynamically adapt to unavailable resources, which may be due to previously allocation to a different emulation job, or for fault tolerance. Relocation of the resources that will execute the emulation job (i.e., “footprint”) may refer to the remapping of a compiled footprint to a revised set of resources, defining a revised footprint. Fault tolerance may refer to support for working around faulty hardware components of the emulation system.

    Dynamic netlist modification of compacted data arrays in an emulation system
    9.
    发明授权
    Dynamic netlist modification of compacted data arrays in an emulation system 有权

    公开(公告)号：US11048843B1

    公开(公告)日：2021-06-29

    申请号：US16217434

    申请日：2018-12-12

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Mitchell G. Poplack ,  Yuhei Hayashi

    IPC: G06F30/331 ,  G06F30/327

    Abstract: A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the subsequent steps. The compaction circuit may also translate the logical read address of the stored data to a physical read address in the shared data array. A dynamic modification engine may enable dynamic modification of netlists while using the compacted data array. In response to a request, the dynamic modification engine may modify one or more keeptags and update read addresses in the control store words.

Patent Agency Ranking