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121 条记录 (耗时 0.042 秒)

    High-Speed Controller for Phase-Change Memory Peripheral Device
    31.
    发明申请
    High-Speed Controller for Phase-Change Memory Peripheral Device 失效
    用于相变存储器外围设备的高速控制器

    公开(公告)号：US20070255891A1

    公开(公告)日：2007-11-01

    申请号：US11770642

    申请日：2007-06-28

    申请人： David Chow ,  Charles Lee ,  Frank Yu

    发明人： David Chow ,  Charles Lee ,  Frank Yu

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0804 ,  G06F12/0238 ,  G06F13/16 ,  G06F13/161 ,  G06F2212/1016 ,  G06F2212/2022 ,  G11C7/10 ,  G11C7/1015 ,  G11C8/08 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2211/5641 ,  G11C2213/79

    摘要： Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Multi-Media Card/Secure Digital (MMC/SD) card. A PCM controller accesses PCM memory devices. Various routines that execute on a CPU in the PCM controller are activated in response to commands in the host-bus transactions. The PCM system increases the throughput of one or more phase-change memory devices by performing one or more of a read-ahead memory operation, a write-ahead memory write operation, a larger page memory write operation, a wider data bus memory write operation, a multi-channel concurrent multi-bank interleaving memory read or write operation, a write-cache memory write operation, and any combination thereof.

    摘要翻译： 外围设备将数据存储在非易失性相变存储器（PCM）中。 PCM单元具有具有高电阻非晶态和低电阻晶体态的合金电阻。 外围设备可以是多媒体卡/安全数字（MMC / SD）卡。 PCM控制器访问PCM存储器设备。 响应于主机总线事务中的命令，激活在PCM控制器中的CPU上执行的各种例程。 PCM系统通过执行预读存储器操作，预写存储器写操作，较大页存储器写操作，更宽数据总线存储器写操作中的一个或多个来增加一个或多个相变存储器件的吞吐量 多通道同时多存储体交错存储器读或写操作，写高速缓存存储器写操作及其任意组合。

    Flash / Phase-Change Memory in Multi-Ring Topology Using Serial-Link Packet Interface
    32.
    发明申请
    Flash / Phase-Change Memory in Multi-Ring Topology Using Serial-Link Packet Interface 失效
    使用串行链路分组接口的多环拓扑中的闪存/相变存储器

    公开(公告)号：US20080016269A1

    公开(公告)日：2008-01-17

    申请号：US11773827

    申请日：2007-07-05

    申请人： David Chow ,  Charles Lee ,  Frank Yu

    发明人： David Chow ,  Charles Lee ,  Frank Yu

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

    摘要： A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.

    摘要翻译： 多环存储器控制器将请求数据包发送到串行闪存芯片的多个环。 多个环中的每个环都具有串行闪存芯片，其具有单向环中的串行链路。 每个串行闪存芯片都具有一个旁路收发器，其中设备ID检查器将串行数据包绕过时钟重新同步器，并且旁路逻辑用于重传到环中的下一个设备，或者当ID为ID时将串行数据包提取给本地设备 匹配发生。 在来自控制器的一次往返事务期间，串行数据包通过环中的所有设备。 由于相同的数据包延迟发生，环路上的所有设备的平均延迟都是恒定的，从而降低了数据相关性能，无论环的数据位置如何。 串行链路可以是外围组件互连（PCI）Express总线。 数据包已经修改了PCI-Express头，定义了数据包类型和数据有效负载长度。

    Two-Level RAM Lookup Table for Block and Page Allocation and Wear-Leveling in Limited-Write Flash-Memories
    33.
    发明申请
    Two-Level RAM Lookup Table for Block and Page Allocation and Wear-Leveling in Limited-Write Flash-Memories 失效
    有限写入闪存中的块和页面分配和磨损均衡的两级RAM查找表

    公开(公告)号：US20070204128A1

    公开(公告)日：2007-08-30

    申请号：US11742270

    申请日：2007-04-30

    申请人： Charles Lee ,  Frank Yu ,  David Chow

    发明人： Charles Lee ,  Frank Yu ,  David Chow

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

    摘要： A restrictive multi-level-cell (MLC) flash memory prohibits regressive page-writes. When a regressive page-write is requested, an empty block having a low wear-level count is found, and data from the regressive page-write and data from pages stored in the old block are written to the empty block in page order. The old block is erased and recycled. A two-level look-up table is stored in volatile random-access memory (RAM). A logical page address from a host is divided by a modulo divider to generate a quotient and a remainder. The quotient is a logical block address that indexes a first-level look-up table to find a mapping entry with a physical block address that selects a row in a second-level look-up table. The remainder locates a column in the row in the second-level look-up table. If any page-valid bits above the column pointed to by the remainder are set, the write is regressive.

    摘要翻译： 限制性多电平单元（MLC）闪存禁止回归页面写入。 当请求回归页面写入时，找到具有低磨损级别计数的空块，并且按页顺序将存储在旧块中的页面写入的数据和来自页面的页面的数据写入空块。 旧区被擦除并回收。 两级查找表存储在易失性随机存取存储器（RAM）中。 来自主机的逻辑页地址由模分隔器除以生成商和余数。 商是一个逻辑块地址，其索引第一级查找表以找到具有在二级查找表中选择行的物理块地址的映射条目。 剩余部分在二级查找表中的行中找到一列。 如果设置了剩余部分指向的列之上的任何页面有效位，则写入是回归的。

    System and method of protecting files from unauthorized modification or deletion
    36.
    发明授权
    System and method of protecting files from unauthorized modification or deletion 失效
    保护文件免遭未经授权的修改或删除的系统和方法

    公开(公告)号：US08239674B2

    公开(公告)日：2012-08-07

    申请号：US11821165

    申请日：2007-06-22

    申请人： Charles Lee ,  David N. Hall, Jr.

    发明人： Charles Lee ,  David N. Hall, Jr.

    IPC分类号： G06F21/00

    CPC分类号： G06F21/6218 ,  G06F2221/2147

    摘要： According to one embodiment of the invention, a method comprises receiving a write request for a file. A temporary file associated with the file is created in response to the write request. A write-lock is applied to the temporary file, namely the file includes a setting that restricts write access to only a component that created or opens the temporary file. Thereafter, the temporary file is closed to disable the write-lock and to enable a component that initiated the write request to access the temporary file.

    摘要翻译： 根据本发明的一个实施例，一种方法包括接收对文件的写入请求。 与该文件相关联的临时文件是响应写请求而创建的。 对临时文件应用写锁定，即该文件包括限制仅对创建或打开临时文件的组件的写访问权限的设置。 此后，临时文件关闭以禁用写锁定，并使启动写请求的组件能够访问临时文件。

    Predictive environment music playlist selection
    38.
    发明授权
    Predictive environment music playlist selection 有权
    预测环境音乐播放列表选择

    公开(公告)号：US08035023B2

    公开(公告)日：2011-10-11

    申请号：US12546913

    申请日：2009-08-25

    申请人： Marcial Hernandez ,  Arne Stoschek ,  Jason Swager ,  Charles Lee

    发明人： Marcial Hernandez ,  Arne Stoschek ,  Jason Swager ,  Charles Lee

    IPC分类号： G10H1/00 ,  G10H1/18

    CPC分类号： G06F17/30755

    摘要： An entertainment system has a music storage system storing a plurality of music pieces, a playback system coupled with the music storage system, a navigation system providing current map information including a present location, wherein a current map has a plurality of zones each being assigned to one of a plurality of zone types, and a controller for controlling playback of selected music pieces, wherein the controller maintains a plurality of playlists, each having a plurality of music pieces and being assigned to at least one zone type. The controller receives information of a present location and a current zone type and selects an assigned playlist, wherein the navigation system further provides information about a distance and/or time to a next zone. The controller modifies the assigned playlist such that a transition to the next zone is timely synchronized with the ending of a music piece of the assigned playlist.

    摘要翻译： 娱乐系统具有存储多个乐曲的音乐存储系统，与音乐存储系统耦合的回放系统，提供包括当前位置的当前地图信息的导航系统，其中当前地图具有多个区域，每个区域被分配到 多个区域类型中的一个，以及用于控制所选音乐片段的重放的控制器，其中控制器保持多个播放列表，每个播放列表具有多个音乐片段并被分配至少一个区域类型。 控制器接收当前位置和当前区域类型的信息，并选择分配的播放列表，其中导航系统进一步向下一个区域提供关于距离和/或时间的信息。 控制器修改分配的播放列表，使得到下一个区域的转换与分配的播放列表的乐曲的结束及时同步。

    Vertical MIM capacitors and method of fabricating the same
    40.
    发明申请
    Vertical MIM capacitors and method of fabricating the same 有权
    垂直MIM电容器及其制造方法

    公开(公告)号：US20070099390A1

    公开(公告)日：2007-05-03

    申请号：US11263419

    申请日：2005-10-31

    申请人： Charles Lee ,  Chi-Hsi Wu

    发明人： Charles Lee ,  Chi-Hsi Wu

    IPC分类号： H01L21/20

    CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L28/55

    摘要： A method of fabricating a vertical MIM capacitor. An insulation layer is formed on the substrate. The insulation layer is patterned to form an opening in a predetermined area of a core electrode. Then, the opening is filled to form a sacrificial plug. Subsequently, the insulation layer is patterned to form a trench in a predetermined area of an outer electrode around the sacrificial plug. A fenced insulation layer is formed around the sacrificial plug simultaneously. After the sacrificial plug is removed, a metal layer is filled in the predetermined area of the core and outer electrodes. A vertical MIM capacitor comprising the core electrode, the fenced insulation layer, and the outer electrode is finally formed. The invention also provides a vertical MIM capacitor.

    摘要翻译： 一种制造垂直MIM电容器的方法。 在基板上形成绝缘层。 将绝缘层图案化以在芯电极的预定区域中形成开口。 然后，填充开口以形成牺牲塞。 随后，将绝缘层图案化以在牺牲插塞周围的外部电极的预定区域中形成沟槽。 围绕牺牲塞同时形成围栏绝缘层。 在去除牺牲塞之后，在芯和外电极的预定区域中填充金属层。 最终形成包括芯电极，围栏绝缘层和外电极的垂直MIM电容器。 本发明还提供一种垂直MIM电容器。