公开(公告)号：US07629213B2

公开(公告)日：2009-12-08

申请号：US11647628

申请日：2006-12-29

申请人： Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung ,  Cheol Mo Jeong

发明人： Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung ,  Cheol Mo Jeong

IPC分类号： H01L21/8238

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.

摘要翻译： 一种制造闪速存储器件的方法包括以下步骤：在半导体衬底上形成用于单元的栅极图案和用于选择晶体管的栅极图案，在包含栅极图案的所得表面上形成缓冲绝缘层，形成绝缘层以形成空隙 用于单元的栅极图案之间的间隔，在绝缘层上形成氮化物层，并且通过间隔物蚀刻工艺在用于选择晶体管的每个栅极图案的一侧上形成间隔物。

公开(公告)号：US20090283818A1

公开(公告)日：2009-11-19

申请号：US12464947

申请日：2009-05-13

申请人： Whee Won Cho ,  Nam Woo So ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Gyeong Jang

发明人： Whee Won Cho ,  Nam Woo So ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Gyeong Jang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, the dielectric layer having a groove for exposing the isolation layer, a trench formed on the isolation layer and exposed through the groove, and a second conductive layer formed over the dielectric layer the trench.

摘要翻译： 闪速存储器件包括形成在半导体衬底的隔离区上的隔离层，形成在半导体衬底的有源区上的隧道绝缘层，形成在隧道绝缘层上的第一导电层，形成在第一 所述绝缘层具有用于暴露所述隔离层的沟槽，形成在所述隔离层上并通过所述沟槽露出的沟槽以及在所述电介质层上形成所述沟槽的第二导电层。

公开(公告)号：US20090098740A1

公开(公告)日：2009-04-16

申请号：US12163328

申请日：2008-06-27

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76232

摘要： The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.

摘要翻译： 本发明公开了一种在半导体器件中形成隔离层的方法。 该方法包括提供其中形成有沟槽的半导体衬底; 在沟槽中形成第一绝缘层; 以及在所述第一绝缘层上形成致密的第二绝缘层。 在上述方法中，在隔离层中不会产生空隙，因此可以减少或防止有源区的弯曲现象来改善半导体的电特性。

公开(公告)号：US20080268612A1

公开(公告)日：2008-10-30

申请号：US11962611

申请日：2007-12-21

申请人： Whee Won Cho ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Suk Joong Kim ,  Jong Hye Cho

发明人： Whee Won Cho ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Suk Joong Kim ,  Jong Hye Cho

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： The present invention discloses to a method of forming an isolation layer in a semiconductor device. In particular, the method of forming an isolation layer in a semiconductor device of the present invention comprises the steps of providing a semiconductor substrate on which a trench is formed; forming spacers on side walls of the trench; forming a first insulating layer to fill a portion of the trench such that a deposition rate on the semiconductor substrate which is a bottom surface of the trench and exposed between the spacers is higher than that on a surface of the space; and forming a second insulating layer on the first insulating layer so as to fill the trench with the second insulating layer. An O3-TEOS layer on the exposed semiconductor substrate which is a bottom surface of the trench is grown faster than that on a surface of the spacer formed of an oxide layer or a nitride layer to prevent the O3-TEOS layers grown on the side walls from coming into contact with each other, and so it is possible to inhibit a generation of a seam and to enhance a gap-filling characteristic for the trench.

摘要翻译： 本发明公开了一种在半导体器件中形成隔离层的方法。 特别地，本发明的半导体器件中形成隔离层的方法包括以下步骤：提供其上形成有沟槽的半导体衬底; 在沟槽的侧壁上形成间隔物; 形成第一绝缘层以填充所述沟槽的一部分，使得作为所述沟槽的底表面并暴露在所述间隔物之间​​的所述半导体衬底上的沉积速率高于所述空间的表面上的沉积速率; 以及在所述第一绝缘层上形成第二绝缘层以便用所述第二绝缘层填充所述沟槽。 作为沟槽底面的暴露的半导体衬底上的O 3 -TOS层比由氧化物层或氮化物层形成的间隔物的表面上生长得快，以防止O 在侧壁上生长的3层以上的层彼此接触，因此可以抑制接缝的产生并且增强沟槽的间隙填充特性。

公开(公告)号：US20080102622A1

公开(公告)日：2008-05-01

申请号：US11647088

申请日：2006-12-27

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho ,  Seong Hwan Myung

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho ,  Seong Hwan Myung

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/3212

摘要： A method of forming a metal line in a semiconductor device, including the steps of forming a metal line in a semiconductor device in which dummy patterns are formed on a dummy region by using non-metal material when a metal line is formed through a damascene process to prevent a formation of an oxide layer on an aluminum layer caused by a slurry and cleaning solution used in the chemical mechanical polishing (CMP) process and carry out an uniform polishing process, whereby it is possible to prevent a digging phenomenon on a metal layer from being generated.

摘要翻译： 一种在半导体器件中形成金属线的方法，包括以下步骤：在通过镶嵌工艺形成金属线时，通过使用非金属材料在虚拟区域上形成虚拟图案的半导体器件中形成金属线 以防止由化学机械抛光（CMP）工艺中使用的浆料和清洗液在铝层上形成氧化物层，并进行均匀的抛光工艺，从而可以防止在金属层上的挖掘现象 从被生成。

公开(公告)号：US20080105983A1

公开(公告)日：2008-05-08

申请号：US11604484

申请日：2006-11-27

申请人： Cheol Mo Jeong ,  Seong Hwan Myung ,  Eun Soo Kim ,  Suk Joong Kim

发明人： Cheol Mo Jeong ,  Seong Hwan Myung ,  Eun Soo Kim ,  Suk Joong Kim

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/53266 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.

摘要翻译： 半导体器件包括第一阻挡金属层和第二阻挡金属层，第三阻挡金属层和金属线。 第一阻挡金属层和第二阻挡金属层形成在半导体衬底上的形成在绝缘层的沟槽的底表面上的绝缘层的顶表面上。 第三阻挡金属层形成在沟槽的侧壁上。 金属线间隙填充沟槽。 在形成半导体器件的金属线的方法中，在半导体衬底上的绝缘层内形成沟槽。 第一阻挡金属层和第二阻挡金属层形成在沟槽的底表面和绝缘层的顶表面上。 第三阻挡金属层形成在沟槽的侧壁上。 金属线间隙填充沟槽。

公开(公告)号：US07482264B2

公开(公告)日：2009-01-27

申请号：US11604484

申请日：2006-11-27

申请人： Cheol Mo Jeong ,  Seong Hwan Myung ,  Eun Soo Kim ,  Suk Joong Kim

发明人： Cheol Mo Jeong ,  Seong Hwan Myung ,  Eun Soo Kim ,  Suk Joong Kim

IPC分类号： H01L21/283

CPC分类号： H01L23/53266 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.

摘要翻译： 半导体器件包括第一阻挡金属层和第二阻挡金属层，第三阻挡金属层和金属线。 第一阻挡金属层和第二阻挡金属层形成在半导体衬底上的形成在绝缘层的沟槽的底表面上的绝缘层的顶表面上。 第三阻挡金属层形成在沟槽的侧壁上。 金属线间隙填充沟槽。 在形成半导体器件的金属线的方法中，在半导体衬底上的绝缘层内形成沟槽。 第一阻挡金属层和第二阻挡金属层形成在沟槽的底表面和绝缘层的顶表面上。 第三阻挡金属层形成在沟槽的侧壁上。 金属线间隙填充沟槽。

公开(公告)号：US07078332B2

公开(公告)日：2006-07-18

申请号：US10880035

申请日：2004-06-29

申请人： Cheol Mo Jeong ,  Tae Kyung Kim

发明人： Cheol Mo Jeong ,  Tae Kyung Kim

IPC分类号： H01L21/4763

CPC分类号： H01L27/105 ,  H01L21/76838 ,  H01L27/1052

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate on which cell strings are formed and in which a plurality of conductive regions are formed; sequentially forming a first interlayer insulation film and a first etch barrier film on the semiconductor substrate; forming a plurality of contact holes by exposing the plurality of conductive regions formed in the semiconductor substrate, wherein an impurity concentration of the conductive regions is reduced due to the process for forming the contact holes; filling a metal material in the contact holes and forming a plurality of contact plugs; sequentially forming a second interlayer insulation film, a second etch barrier film and a third interlayer insulation film over a resulting structure including the contact plugs; forming a plurality of metal line patterns, wherein the metal line patterns pass through the third interlayer insulation film, the second etch barrier film and the second interlayer insulation film and contact to the contact plugs; forming a fourth interlayer insulation film over a resulting structure including the plurality of metal line patterns; forming a plurality of metal line contact holes by patterning the fourth interlayer insulation film; and forming a plurality of metal line contact plugs in the plurality of metal line contact holes by filling a metal material in the metal line contact holes.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括以下步骤：提供其上形成有多个导电区域的半导体衬底，其上形成有多个导电区域; 在半导体衬底上依次形成第一层间绝缘膜和第一蚀刻阻挡膜; 通过暴露形成在半导体衬底中的多个导电区域来形成多个接触孔，其中由于形成接触孔的工艺导致导电区域的杂质浓度降低; 在接触孔中填充金属材料并形成多个接触插塞; 在包括接触塞的所得结构上依次形成第二层间绝缘膜，第二蚀刻阻挡膜和第三层间绝缘膜; 形成多个金属线图案，其中所述金属线图案通过所述第三层间绝缘膜，所述第二蚀刻阻挡膜和所述第二层间绝缘膜并与所述接触插塞接触; 在包括所述多个金属线图案的所得结构上形成第四层间绝缘膜; 通过图案化第四层间绝缘膜形成多个金属线接触孔; 以及通过在金属线接触孔中填充金属材料在所述多个金属线接触孔中形成多个金属线接触塞。

公开(公告)号：US06579789B2

公开(公告)日：2003-06-17

申请号：US09880055

申请日：2001-06-14

申请人： Cheol Mo Jeong

发明人： Cheol Mo Jeong

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/28518 ,  H01L23/485 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the method for fabricating a metal wiring, an insulation film is formed on a semiconductor substrate. The insulation film has a contact hole exposing the semiconductor substrate. A Ti—Si film is formed over the silicon substrate, and a Ti—Si—N film is formed on the Ti—Si film. The contact hole is then filled by depositing copper on the Ti—Si—N film, and a silicon nitride film is formed over the silicon substrate.

公开(公告)号：US07365430B2

公开(公告)日：2008-04-29

申请号：US11027153

申请日：2004-12-30

申请人： Cheol Mo Jeong

发明人： Cheol Mo Jeong

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/7842

摘要： Disclosed herein is a semiconductor device and method of manufacturing the same. A step between a memory cell formed in a cell region and a transistor formed in a peripheral circuit region is minimized, and the height of a gate in the memory cell is minimized. Accordingly, subsequent processes are facilitated and the electrical property of the device is thus improved.

摘要翻译： 这里公开了半导体装置及其制造方法。 在单元区域中形成的存储单元和形成在外围电路区域中的晶体管之间的步骤最小化，并且使存储单元中的栅极的高度最小化。 因此，便于后续的处理，从而提高了器件的电性能。