公开(公告)号：US06845444B2

公开(公告)日：2005-01-18

申请号：US09934574

申请日：2001-08-23

申请人： Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

发明人： Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

IPC分类号： G06F3/00 ,  G06F9/24 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4004 ,  G06F13/423 ,  G06F2213/0024

摘要： A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state. Subsequently, the configuration value fetched from the non-volatile memory is asserted to the at least one configurable device to configure the configurable device, and then the processor reset signal is deasserted, and the at least one configurable device is thereby completely configured.

摘要翻译： 提供了一种减少具有至少一个可配置设备的计算机系统中的捆扎设备的方法，其包括以下步骤。 首先提供存储在非易失性存储器中的配置值。 在计算机系统的上电和复位期间，高速外设总线的处理器复位信号和总线复位信号都被断言，其中高速外设总线被包括在计算机系统中。 当高速外设总线的工作时钟达到其工作电压和频率时，从非易失性存储器中取出配置值。 取出步骤被重复，直到获取的配置值的最高有效位（MSB）从第一状态改变到第二状态。 随后，从非易失性存储器取出的配置值被断言给至少一个可配置设备以配置可配置设备，然后解除处理器复位信号，并且由此完全配置至少一个可配置设备。

公开(公告)号：US06643718B1

公开(公告)日：2003-11-04

申请号：US09621070

申请日：2000-07-21

申请人： Chao-Yu Chen ,  Hui-Neng Chang ,  Sui-His Chu

发明人： Chao-Yu Chen ,  Hui-Neng Chang ,  Sui-His Chu

IPC分类号： G06F9315

CPC分类号： G06F7/00 ,  G06F9/52 ,  G06F9/522

摘要： A barrier control scheme controls the order dependency of items in a multiple FIFO queue structure. The barrier control scheme includes a cycle ID generator, a barrier bit/barrier ID generator and a cycle ID and barrier ID comparator. Each incoming item to the FIFOs is assigned a cycle ID. If an incoming item of a first FIFO has order dependency on items of a second FIFO, a barrier bit is set and a barrier ID is determined and generated by the barrier bit/barrier ID generator. The barrier bit and barrier ID are inserted in the first FIFO along with other fields of the incoming item. When an item is to be consumed, the cycle ID and barrier ID comparator compares its barrier ID and the cycle IDs of items in the second FIFO. The item to be consumed is blocked until all items on which the item is dependent are consumed in the second FIFO.

摘要翻译： 障碍控制方案控制多FIFO队列结构中项目的顺序依赖性。 屏障控制方案包括循环ID发生器，屏障位/屏障ID发生器和周期ID和屏障ID比较器。 每个进入FIFO的输入项都被分配一个循环ID。 如果第一FIFO的输入项目具有与第二FIFO的项目有顺序依赖关系，则设置障碍位并且屏障ID /屏障ID发生器确定并产生屏障ID。 屏障位和屏障ID与输入项目的其他字段一起插入第一个FIFO。 当一个物品被消耗时，循环ID和屏障ID比较器比较其屏障ID和第二个FIFO中项目的循环ID。 要消费的项目被阻止，直到所有项目依赖的项目在第二个FIFO中被消耗。