公开(公告)号：US07772072B2

公开(公告)日：2010-08-10

申请号：US11845945

申请日：2007-08-28

Applicant: Szu-Yu Wang ,  Hang-Ting Lue

Inventor： Szu-Yu Wang ,  Hang-Ting Lue

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/4234

Abstract: A non-volatile memory located on a substrate is provided. The non-volatile memory includes a tunnel layer, a charge trapping composite layer, a gate and a source/drain region. The tunnel layer is located on the substrate, the charge trapping composite layer is located on the tunnel layer and the gate is located over the charge trapping composite layer. The source/drain region is located in the substrate on both sides of the tunnel layer. With the charge trapping composite layer, the non-volatile memory has relatively better programming and erasing performance and higher data retention ability. Furthermore, since there is no need to perform a thermal process in the formation of the charge trapping composite layer, thermal budget of the manufacturing process is low.

Abstract translation: 提供位于基板上的非易失性存储器。 非易失性存储器包括隧道层，电荷俘获复合层，栅极和源极/漏极区域。 隧道层位于衬底上，电荷捕获复合层位于隧道层上，栅极位于电荷捕获复合层上。 源极/漏极区位于隧道层两侧的衬底中。 通过电荷捕获复合层，非易失性存储器具有相对更好的编程和擦除性能以及更高的数据保留能力。 此外，由于不需要在电荷捕获复合层的形成中进行热处理，因此制造工艺的热预算低。

公开(公告)号：US20090114976A1

公开(公告)日：2009-05-07

申请号：US12338751

申请日：2008-12-18

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L29/792

CPC classification number: G11C16/0466 ,  G11C16/10 ,  G11C16/3468

Abstract: A method for programming and erasing charge-trapping memory device is provided. The method includes applying a first negative voltage to a gate causing a dynamic balance state (RESET\ERASE state). Next, a positive voltage is applied to the gate to program the device. Then, a second negative voltage is applied to the gate to restore the device to the RESET\ERASE state.

Abstract translation: 提供了一种用于编程和擦除电荷俘获存储器件的方法。 该方法包括将第一负电压施加到导致动态平衡状态的门（RESET \ ERASE状态）。 接下来，向门施加正电压以对器件进行编程。 然后，第二个负电压被施加到门以将器件恢复到RESET \ ERASE状态。

公开(公告)号：US20090057752A1

公开(公告)日：2009-03-05

申请号：US11845945

申请日：2007-08-28

Applicant: Szu-Yu Wang ,  Hang-Ting Lue

Inventor： Szu-Yu Wang ,  Hang-Ting Lue

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/4234

Abstract: A non-volatile memory located on a substrate is provided. The non-volatile memory includes a tunnel layer, a charge trapping composite layer, a gate and a source/drain region. The tunnel layer is located on the substrate, the charge trapping composite layer is located on the tunnel layer and the gate is located over the charge trapping composite layer. The source/drain region is located in the substrate on both sides of the tunnel layer. With the charge trapping composite layer, the non-volatile memory has relatively better programming and erasing performance and higher data retention ability. Furthermore, since there is no need to perform a thermal process in the formation of the charge trapping composite layer, thermal budget of the manufacturing process is low.

Abstract translation: 提供位于基板上的非易失性存储器。 非易失性存储器包括隧道层，电荷俘获复合层，栅极和源极/漏极区域。 隧道层位于衬底上，电荷捕获复合层位于隧道层上，栅极位于电荷捕获复合层上。 源极/漏极区位于隧道层两侧的衬底中。 通过电荷捕获复合层，非易失性存储器具有相对更好的编程和擦除性能以及更高的数据保留能力。 此外，由于不需要在电荷捕获复合层的形成中进行热处理，因此制造工艺的热预算低。

公开(公告)号：US20090039416A1

公开(公告)日：2009-02-12

申请号：US11845321

申请日：2007-08-27

Applicant: Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

Inventor： Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792

Abstract: A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

Abstract translation: 带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括 通道由工程隧道电介质。

公开(公告)号：US07391652B2

公开(公告)日：2008-06-24

申请号：US11381760

申请日：2006-05-05

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/0466 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427

Abstract: A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.

Abstract translation: 一种用于p沟道存储单元的编程方法，所述存储单元包括源极，漏极和栅极。 门施加第一电压，这导致Fowler-Nordheim（-FN）空穴注入，从而使存储器单元处于编程状态。

公开(公告)号：US20080116506A1

公开(公告)日：2008-05-22

申请号：US11756559

申请日：2007-05-31

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.

Abstract translation: 一种存储单元，包括：具有表面的半导体衬底，源极区和漏极区设置在衬底的表面下方并被沟道区分开; 设置在沟道区域上方的具有大于3纳米的有效氧化物厚度的隧道势垒介电结构; 导电层，设置在隧道势垒电介质结构之上并在沟道区之上; 电荷捕获结构，设置在导电层之上并在沟道区上方; 位于所述电荷俘获结构上方且位于所述沟道区上方的顶部电介质结构; 以及设置在顶部电介质结构之上和沟道区上方的顶部导电层以及其制造方法和制造方法。

公开(公告)号：US20080087942A1

公开(公告)日：2008-04-17

申请号：US11785322

申请日：2007-04-17

Applicant: Tzu-Hsuan Hsu ,  Hang-Ting Lue

Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC: H01L29/792 ,  G11C11/34 ,  H01L21/336

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/785 ,  H01L29/792

Abstract: A vertical channel memory including a substrate, a channel, a multi-layer structure, a gate, a first terminal and a second terminal is provided. The channel is protruded from the substrate and has a top surface and two vertical surfaces. The multi-layer structure is disposed on the two vertical surfaces of the channel. The gate straddling multi-layer structure is positioned above the two vertical surfaces of the channel. The first terminal and the second terminal are respectively positioned at two sides of the channel opposing to the gate.

Abstract translation: 提供了包括基板，通道，多层结构，栅极，第一端子和第二端子的垂直沟道存储器。 通道从基板突出并具有顶表面和两个垂直表面。 多层结构设置在通道的两个垂直表面上。 栅极跨层多层结构位于通道的两个垂直表面上方。 第一端子和第二端子分别位于与栅极相对的通道的两侧。

公开(公告)号：US20080079064A1

公开(公告)日：2008-04-03

申请号：US11898528

申请日：2007-09-13

Applicant: Sheng-Chih Lai ,  Hang-Ting Lue

Inventor： Sheng-Chih Lai ,  Hang-Ting Lue

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/517 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.

Abstract translation: 提供了具有非易失性存储器的半导体器件及其制造方法。 半导体器件包括基底材料和堆叠结构。 设置在基材上的堆叠结构至少包括隧穿层，捕获层和电介质层。 捕获层设置在隧道层上。 电介质层具有介电常数并且设置在捕获层上。 当电介质层进行处理时，电介质层从第一固态转变为第二固态。

公开(公告)号：US20080002477A1

公开(公告)日：2008-01-03

申请号：US11836142

申请日：2007-08-09

Applicant: Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

Inventor： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC: G11C11/34 ,  H01L21/36

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

Abstract: The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

Abstract translation: 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US07315474B2

公开(公告)日：2008-01-01

申请号：US11324581

申请日：2006-01-03

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C11/34

CPC classification number: H01L29/792 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/265 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.

Abstract translation: 存储单元包括：半导体衬底，其具有设置在衬底的表面下方并由沟道区分隔开的源极区和漏极区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括至少一层具有小的空穴隧道势垒高度的层; 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且描述设置在绝缘层上方的栅极电极及其阵列和操作方法。