公开(公告)号：US08309437B2

公开(公告)日：2012-11-13

申请号：US12450295

申请日：2008-02-26

申请人： Christophe Figuet ,  Oleg Kononchuk

发明人： Christophe Figuet ,  Oleg Kononchuk

IPC分类号： H01L21/20

CPC分类号： H01L21/02433 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262

摘要： The present invention relates to method of fabricating a (110) oriented silicon substrate and to a method of fabricating a bonded pair of substrates comprising such a (110) oriented silicon substrate. The invention further relates to a silicon substrate with (110) orientation and to a bonded pair of silicon substrates comprising a first silicon substrate with (100) orientation and a second silicon substrate with (110) orientation. Methods include the steps of providing a basic silicon substrate with (110) orientation, the basic silicon substrate having a roughness being equal or less than 0.15 nm RMS, and depositing epitaxially a silicon layer with (110) orientation on the basic silicon substrate at a pressure between 40 Torr to 120 Torr, and at a temperature between about 1000° C. and about 1200° C. and using trichlorosilane or dichlorosilane as silicon precursor gas.

摘要翻译： 本发明涉及一种制造（110）定向硅衬底的方法以及一种制造包括这种（110）定向硅衬底的粘结对衬底对的方法。 本发明还涉及具有（110）取向的硅衬底和包括具有（100）取向的第一硅衬底和具有（110）取向的第二硅衬底的键合的一对硅衬底。 方法包括以下步骤：提供具有（110）取向的基本硅衬底，所述碱性硅衬底具有等于或小于0.15nm RMS的粗糙度，并且在基底硅衬底上以（110）取向外延地沉积（110）取向的硅层， 压力在40托至120托之间，在约1000℃至约1200℃之间的温度下，并使用三氯硅烷或二氯硅烷作为硅前体气体。

公开(公告)号：US07772127B2

公开(公告)日：2010-08-10

申请号：US11267494

申请日：2005-11-03

申请人： Christophe Figuet ,  Mark Kennard

发明人： Christophe Figuet ,  Mark Kennard

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76254 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02524 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262

摘要： The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.

摘要翻译： 本发明涉及一种用于通过向第一面内晶格参数a1提供衬底来形成半导体异质结构的方法，为缓冲层提供第二面内晶格参数a2并在缓冲层上提供顶层。 为了改善半导体异质结构的表面粗糙度，在缓冲层和顶层之间提供附加层，其中附加层具有在第一和第二晶格参数之间的第三面内晶格参数a3 。

公开(公告)号：US07387953B2

公开(公告)日：2008-06-17

申请号：US11146572

申请日：2005-06-06

申请人： Christophe Figuet

发明人： Christophe Figuet

IPC分类号： H01L21/00

CPC分类号： H01L21/02507 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262

摘要： The invention relates to a laminated layer structure that includes a substrate and a stack of a plurality of layers of a material that includes at least two compounds A and B, wherein compound A has a crystalline structure being sufficient to allow a homo- or heteroepitaxial growth of compound A on the substrate, and wherein at least a part of the layers of the stack have a gradient composition AxB(1-xg), with x being a composition parameter within the range of 0 and 1 and with the composition parameter (1-xg) increasing gradually, in particular linearly, over the thickness of the corresponding layer. In order to improve the quality of the laminated layer structure with respect to the surface roughness and dislocation density, the composition parameter at the interface between the layer in the stack with the gradient composition and the subsequent layer in the stack is chosen to be smaller than the composition parameter (1-xg) of the layer with a gradient composition. The invention also relates to a method to fabricate such a laminated layer structure.

摘要翻译： 本发明涉及层压层结构，其包括基材和包含至少两种化合物A和B的多层材料的叠层，其中化合物A具有足以允许同质或异质外延生长的晶体结构 的化合物A，并且其中堆叠的至少一部分层具有梯度组合物A x B（1-x g），其中x是 组成参数在0和1的范围内，并且组成参数（1-x＆lt;＆gt;＆gt;）在相应层的厚度上逐渐增加，特别是线性增加。 为了提高相对于表面粗糙度和位错密度的叠层结构的质量，将层叠层与梯度组成之间的界面处的组成参数和堆叠中的后续层选择为小于 具有梯度组成的层的组成参数（1-x g g）。 本发明还涉及制造这种叠层结构的方法。

公开(公告)号：US20080132031A1

公开(公告)日：2008-06-05

申请号：US11674392

申请日：2007-02-13

申请人： Cecile Aulnette ,  Christophe Figuet ,  Nicolas Daval

发明人： Cecile Aulnette ,  Christophe Figuet ,  Nicolas Daval

IPC分类号： H01L21/00

CPC分类号： H01L21/76254 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262

摘要： A method for manufacturing a semiconductor heterostructure by first manufacturing a donor wafer having a first substrate with a first in-plane lattice parameter, a spatially graded buffer layer having a second in-plane lattice parameter, and a strained smoothing layer of a semiconductor material having a third in-plane lattice parameter which has a value between that of the first and second lattice parameters. A top layer is formed on the ungraded layer a top layer of a semiconductor material having a top surface, optionally with a superficial layer present on the top surface and having a thickness that is equal to or smaller than 10 nanometers. Next, a handle wafer of a second substrate having an insulator layer thereon is bonded with the donor wafer in such way that (a) the insulator layer of the handle wafer is bonded directly onto the top surface of the top layer of the donor wafer, or (b) the insulator layer of the handle wafer is bonded onto the superficial layer.

摘要翻译： 一种半导体异质结构的制造方法，首先制造具有第一面内晶格参数的第一衬底的施主晶片，具有第二面内晶格参数的空间渐变缓冲层，以及半导体材料的应变平滑化层， 具有第一和第二格子参数之间的值的第三平面晶格参数。 顶层在未分级层上形成具有顶表面的半导体材料的顶层，任选具有位于顶表面上的表层，并具有等于或小于10纳米的厚度。 接下来，其上具有绝缘体层的第二衬底的处理晶片与施主晶片接合，使得（a）把手晶片的绝缘体层直接接合到施主晶片顶层的顶表面上， 或者（b）把手晶片的绝缘体层结合到表面层上。

公开(公告)号：US20080017952A1

公开(公告)日：2008-01-24

申请号：US11491616

申请日：2006-07-24

申请人： Nyles W. Cody ,  Christophe Figuet ,  Mark Kennard

发明人： Nyles W. Cody ,  Christophe Figuet ,  Mark Kennard

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532

摘要： A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate

摘要翻译： 包括衬底的半导体工件，包括形成在衬底上的渐变部分的松弛缓冲层以及缓和缓冲层的渐变部分内的至少一个应变过渡层及其制造方法。 至少一个应变过渡层由于松弛缓冲层相对于衬底的CTE收缩的差热膨胀系数（CTE）收缩而减少了工件弓的数量