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31.发明授权Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types 失效半导体制造分辨率增强系统和方法，用于同时构图不同的特征类型公开(公告)号：US06994939B1
公开(公告)日：2006-02-07
申请号：US10283685
申请日：2002-10-29
IPC分类号： G03F9/00
摘要： A method and system of making a mask with a transparent substrate thereon is provided. A first resolution enhancement structure is formed on the first portion of the transparent substrate. A second resolution enhancement structure is formed on a second portion of the transparent substrate, with the second resolution enhancement structure different from the first resolution enhancement structure.
摘要翻译： 提供了一种制造其上具有透明基板的掩模的方法和系统。 在透明基板的第一部分上形成第一分辨率增强结构。 第二分辨率增强结构形成在透明基板的第二部分上，第二分辨率增强结构不同于第一分辨率增强结构。
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32.发明授权Method for self-aligning polysilicon gates with field isolation and the resultant structure 失效使用场隔离自对准多晶硅栅极的方法及其结果
公开(公告)号：US6046088A
公开(公告)日：2000-04-04
申请号：US985400
申请日：1997-12-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762
CPC分类号： H01L21/28123 , H01L21/76224 , H01L29/6659
摘要： A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.
摘要翻译： 在诸如浅氧化物沟槽的半导体衬底（例如浅氧化物沟槽）中形成场隔离的方法，用于隔离包括互补FET（例如CMOS）的FET晶体管，所述沟槽的选定部分在衬底上延伸并与随后形成的上表面共面 多晶硅门 在沟槽开口的形成和填充期间使用蚀刻保护层，使得沟槽的顶部与蚀刻保护层的上表面共面。 在将非掩蔽沟槽平坦化到蚀刻保护层的底部边缘之前，将沟槽的选定部分进行掩模和保护。 在多晶硅的沉积和平坦化之后，用于形成FET晶体管的多晶硅栅极的沉积多晶硅层的上表面与场隔离沟槽的向上延伸的选定部分是共面的和自对准的。
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公开(公告)号：US5928813A
公开(公告)日：1999-07-27
申请号：US684506
申请日：1996-07-19
IPC分类号： G03F1/32 , H01L21/027 , G03F9/00
CPC分类号： G03F1/32
摘要： An attenuated phase shift mask comprises a first layer having a thickness to provide a transmission in the range of about 3 to 10% formed on a transparent substrate and a second layer comprising a transparent material having a thickness to provide a desired phase shift, formed on said first layer. For a phase shift of 180.degree. and i-line wavelength (365 nm) where chromium is used as the first layer, then a thickness within the range of about 25 to 75 nm is employed; where silicon dioxide is used as the second layer; then a thickness of about 400 to 450 nm is employed. While the oxide may be dry-etched, an isotropic wet etch provides superior aerial images.
摘要翻译： 衰减相移掩模包括第一层，其具有提供在透明衬底上形成的大约3至10％范围内的透射率的厚度，以及包括具有提供期望相移的厚度的透明材料的第二层，形成在 说第一层。 对于使用铬作为第一层的180°和i线波长（365nm）的相移，则使用在约25nm至75nm范围内的厚度; 其中使用二氧化硅作为第二层; 然后使用约400至450nm的厚度。 虽然氧化物可以被干蚀刻，但是各向同性的湿蚀刻提供了优异的航空图像。
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公开(公告)号：US07120285B1
公开(公告)日：2006-10-10
申请号：US09515348
申请日：2000-02-29
CPC分类号： G03F1/70
摘要： A method of evaluating a wafer structure formation process includes extracting the outline of an actual mask pattern, and simulating a lithographic process using the actual mask pattern to obtain a simulated wafer structure. The extracting the outline of the actual mask pattern may include, for example, imaging the actual mask using a scanning electron microscope (SEM). A second simulated wafer structure may also be obtained, by simulating the lithographic process using the ideal mask pattern design that was used in producing the actual mask pattern. Thus the relative contribution of mask pattern effects to overall wafer proximity effects may be evaluated by comparing the two simulated wafer structures, either with each other or against a benchmark such as a desired, ideal structure. This information may then be used to generate optical proximity correction (OPC) mask designs which compensate for mask patterning errors and give better wafer performance. The simulated wafer structures may be overlaid upon one another to allow for a direct comparison and full analysis of CD variations.
摘要翻译： 评估晶片结构形成处理的方法包括提取实际掩模图案的轮廓，并且使用实际掩模图案来模拟光刻处理以获得模拟的晶片结构。 提取实际掩模图案的轮廓可以包括例如使用扫描电子显微镜（SEM）对实际掩模进行成像。 也可以通过使用用于生产实际掩模图案的理想掩模图案设计来模拟光刻工艺来获得第二模拟晶片结构。 因此，掩模图案效应对整个晶片接近效应的相对贡献可以通过比较两个模拟晶片结构彼此或与诸如期望的理想结构之类的基准来评估。 然后可以使用该信息来产生补偿掩模图案化错误并提供更好的晶片性能的光学邻近校正（OPC）掩模设计。 模拟的晶片结构可以彼此重叠以允许CD变化的直接比较和全面分析。
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公开(公告)号：US06627355B2
公开(公告)日：2003-09-30
申请号：US09742970
申请日：2000-12-20
IPC分类号： G03F900
摘要： The present invention provides a method of and system for reducing the absorption of light by opaque material in a photomask. The method includes providing a photomask substrate, and applying an opaque material to one side of the photomask substrate. The interface between the opaque material and photomask substrate reflects at least 80 percent of the light through the photomask.
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公开(公告)号：US5766804A
公开(公告)日：1998-06-16
申请号：US702057
申请日：1996-08-23
IPC分类号： G03F1/00 , G03F7/20 , G03F9/00 , H01L21/027
CPC分类号： G03F7/70283 , G03F1/26 , G03F1/34 , G03F1/70 , G03F7/70433
摘要： A method of performing poly level lithography in manufacturing an integrated circuit using a phase shift mask in a step and repeat optical tool where the phase assignment for said phase shift mask is determined by a technique which determines, without assignment conflict, the Intersection of the gate pattern with the active gate pattern and which divides the Intersection into categories of stacks where a slightly different phase assignment rules is employed for the different stacks.
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37.发明授权Mask for optical lithography using phase shift masking and integrated circuit produced therefrom 失效使用相移掩模和由其制成的集成电路进行光刻的掩模
公开(公告)号：US5702848A
公开(公告)日：1997-12-30
申请号：US702058
申请日：1996-08-23
IPC分类号： G03F1/00 , G03F7/20 , G03F9/00 , H01L21/027
CPC分类号： G03F7/70283 , G03F1/26 , G03F1/34 , G03F1/70 , G03F7/70433
摘要： A method of performing poly level lithography in manufacturing an integrated circuit using a phase shift mask in a step and repeat optical tool where the phase assignment for said phase shift mask is determined by a technique which determines, without assignment conflict, the Intersection of the gate pattern with the active gate pattern and which divides the Intersection into categories of stacks where a slightly different phase assignment rules is employed for the different stacks.
摘要翻译： 在步骤中使用相移掩模制造集成电路的制造集成电路的方法和重复光学工具，其中用于所述相移掩模的相位分配由一种技术来确定，所述技术在没有分配冲突的情况下确定栅极的交点 模式与有源栅格图案，并将交点划分为堆栈类别，其中对不同堆栈采用略微不同的相位分配规则。
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公开(公告)号：US5573890A
公开(公告)日：1996-11-12
申请号：US276734
申请日：1994-07-18
IPC分类号： G03F1/00 , G03F7/20 , G03F9/00 , H01L21/027
CPC分类号： G03F7/70283 , G03F1/26 , G03F1/34 , G03F1/70 , G03F7/70433
摘要： A method of performing poly level lithography in manufacturing an integrated circuit using a phase shift mask in a step and repeat optical tool where the phase assignment for said phase shift mask is determined by a technique which determines, without assignment conflict, the Intersection of the gate pattern with the active gate pattern and which divides the Intersection into categories of stacks where a slightly different phase assignment rule is employed for the different stacks.
摘要翻译： 在步骤中使用相移掩模制造集成电路的制造集成电路的方法和重复光学工具，其中用于所述相移掩模的相位分配由一种技术来确定，所述技术在没有分配冲突的情况下确定栅极的交点 模式与有源栅极图案，并将交点分成堆栈类别，其中对于不同的堆栈采用略微不同的相位分配规则。
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