公开(公告)号：US08119310B1

公开(公告)日：2012-02-21

申请号：US12872938

申请日：2010-08-31

Applicant: Lee-Chung Lu ,  Yi-Kan Cheng ,  Hsiao-Shu Chao ,  Ke-Ying Su ,  Cheng-Hung Yeh ,  Dian-Hau Chen ,  Ru-Gun Liu ,  Wen-Chun Huang

Inventor： Lee-Chung Lu ,  Yi-Kan Cheng ,  Hsiao-Shu Chao ,  Ke-Ying Su ,  Cheng-Hung Yeh ,  Dian-Hau Chen ,  Ru-Gun Liu ,  Wen-Chun Huang

IPC: G03F9/00 ,  G06F17/50

CPC classification number: G03F1/70

Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.

Abstract translation: 一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模 。 确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。 对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。

公开(公告)号：US08001494B2

公开(公告)日：2011-08-16

申请号：US12250424

申请日：2008-10-13

Applicant: Yung-Chin Hou ,  Ying-Chou Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yi-Kan Cheng ,  Chung-Kai Lin ,  Hsiao-Shu Chao ,  Ping-Heng Yeh ,  Min-Hong Wu ,  Yao-Ching Ku ,  Tsong-Hua Ou

Inventor： Yung-Chin Hou ,  Ying-Chou Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yi-Kan Cheng ,  Chung-Kai Lin ,  Hsiao-Shu Chao ,  Ping-Heng Yeh ,  Min-Hong Wu ,  Yao-Ching Ku ,  Tsong-Hua Ou

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5081

Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

Abstract translation: 公开了一种用于集成电路设计和后期布局分析的系统和方法。 集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

公开(公告)号：US20110119648A1

公开(公告)日：2011-05-19

申请号：US12649979

申请日：2009-12-30

Applicant: Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.

Abstract translation: 一种方法包括接收要包括在IC布局中的多个电路部件的标识。 生成表示连接两个电路部件的第一图案的数据。 第一图案具有多个片段。 至少两个片段具有彼此垂直的纵向方向。 保留与至少两个段中的至少一个相邻的至少一个无图案区域。 生成表示在第一图案附近的一个或多个附加图案的数据。 在无模式区域中没有形成附加图案。 第一种图案和附加图案形成双重图案化顺应的图案集合。 将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

公开(公告)号：US20110035717A1

公开(公告)日：2011-02-10

申请号：US12846594

申请日：2010-07-29

Applicant: Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu Alex Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

Inventor： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu Alex Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072

Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

Abstract translation: 本发明的实施例是一种用于提供集成电路布局的经调整的电子表示的计算机程序产品。 计算机程序产品具有其上体现计算机程序的介质。 此外，计算机程序包括用于从完整节点网表提供全节点单元的计算机程序代码，用于缩放全节点单元以提供收缩节点单元的计算机程序代码，用于提供全节点单元的定时性能的计算机程序代码和 收缩节点单元，用于将全节点单元的定时性能与收缩节点单元的定时性能进行比较的计算机程序代码以及用于提供第一网表的计算机程序代码。

公开(公告)号：US20100199238A1

公开(公告)日：2010-08-05

申请号：US12617046

申请日：2009-11-12

Applicant: Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

Inventor： Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

Abstract translation: 一种用于集成电路设计的方法包括提供集成电路的布局; 确定集成电路的关键参数; 确定关键参数的目标值; 并且使用第一收缩百分比来执行布局的第一收缩以产生收缩的布局。 通过从缩小布局生成关键参数的值来评估收缩布局。 找到关键参数的值的一部分不能满足相应的目标值。 提供用于调整缩小布局的制造过程的指南，使得关键参数的值的部分可以满足相应的目标值。

公开(公告)号：US07467365B2

公开(公告)日：2008-12-16

申请号：US11521095

申请日：2006-09-14

Applicant: George H. Chang ,  Yi-Kan Cheng ,  Chen-Teng Fan ,  Chen-Lin Yang ,  Yung-Chin Hou ,  Chu-Ping James Wang

Inventor： George H. Chang ,  Yi-Kan Cheng ,  Chen-Teng Fan ,  Chen-Lin Yang ,  Yung-Chin Hou ,  Chu-Ping James Wang

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising automatically reading one or more netlists, identifying one or more sub-circuits in the netlists isomorphic to at least one of predefined sub-circuits, identifying one or more device parameters for sanity checking the identified sub-circuits, and comparing the identified device parameters against the predefined checking criteria.

公开(公告)号：US20070266360A1

公开(公告)日：2007-11-15

申请号：US11688692

申请日：2007-03-20

Applicant: Yi-Kan Cheng ,  Ke-Ying Su ,  Victor C. Y. Chang

Inventor： Yi-Kan Cheng ,  Ke-Ying Su ,  Victor C. Y. Chang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: An integrated circuit (IC) design method includes providing a design layout defined in a plurality of grids; simulating a chemical mechanical polishing (CMP) process to an IC substrate with a patterned structure defined by the design layout, generating a dielectric thickness and a metal thickness on one of the plurality of grids; extracting a capacitance based on the dielectric thickness on the one of the plurality of grids; and extracting a resistance based on the metal thickness on the one of the plurality of grids.

Abstract translation: 集成电路（IC）设计方法包括提供在多个网格中定义的设计布局; 模拟化学机械抛光（CMP）工艺到具有由设计布局限定的图案化结构的IC衬底，在所述多个栅格之一上产生电介质厚度和金属厚度; 基于所述多个栅格中的所述一个栅极上的电介质厚度提取电容; 以及基于所述多个网格中的所述一个网格上的金属厚度提取电阻。

公开(公告)号：US20070266356A1

公开(公告)日：2007-11-15

申请号：US11688654

申请日：2007-03-20

Applicant: Gwan Sin Chang ,  Yi-Kan Cheng ,  Ivy Chiu ,  Ke-Ying Su

Inventor： Gwan Sin Chang ,  Yi-Kan Cheng ,  Ivy Chiu ,  Ke-Ying Su

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5031 ,  G06F2217/12 ,  Y02P90/265

Abstract: An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.

Abstract translation: 集成电路（IC）设计方法包括提供IC设计布局数据; 基于IC设计布局模拟化学机械抛光（CMP）工艺到材料层，以产生各种几何参数; 根据CMP工艺仿真的各种几何参数提取电阻和电容; 并且基于所提取的电阻和电容来执行电路定时分析。

公开(公告)号：US20070266352A1

公开(公告)日：2007-11-15

申请号：US11689197

申请日：2007-03-21

Applicant: Yi-Kan Cheng ,  Chih-Ming Lai ,  Ru-Gun Liu

Inventor： Yi-Kan Cheng ,  Chih-Ming Lai ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Efficient and cost-effective systems and methods for detecting and correcting hot spots of semiconductor devices are disclosed. In one aspect, a method for creating a layout from a circuit design is described. The method includes applying a first set of hot spot conditions to a global route to produce a detailed route; applying a second set of hot spot conditions to the detailed route to produce a post-detailed route; and applying a third set of hot spot conditions to the post-detailed route to produce the layout. In another aspect, a method includes providing a circuit design; applying a first hot spot filter to a global routing of the circuit design to produce a detailed route; applying a less pessimistic, second hot spot filter to the detailed route to produce a post-detailed route; and performing a rip-up and reroute of the post-detailed route to produce a final layout.

Abstract translation: 公开了用于检测和校正半导体器件的热点的高效且成本有效的系统和方法。 在一个方面，描述了一种用于从电路设计创建布局的方法。 该方法包括将第一组热点条件应用于全局路由以产生详细路由; 将第二组热点条件应用于详细路线以产生后详细路线; 以及将第三组热点条件应用于后详细路线以产生布局。 另一方面，一种方法包括提供电路设计; 将第一热点滤波器应用于电路设计的全局路由以产生详细的路由; 在详细的路线上应用较不悲观的第二热点过滤器，以产生详细的路线; 并执行后期详细路线的撤销和重新路线以产生最终布局。

公开(公告)号：US20070266248A1

公开(公告)日：2007-11-15

申请号：US11687384

申请日：2007-03-16

Applicant: Yi-Kan Cheng ,  Gwan Sin Chang ,  Jill Liu ,  Hsiao-Shu Chiao

Inventor： Yi-Kan Cheng ,  Gwan Sin Chang ,  Jill Liu ,  Hsiao-Shu Chiao

IPC: H04L9/00

CPC classification number: H04L9/00 ,  G06F21/72 ,  H04L2209/12

Abstract: An encryption and decryption interface for integrated circuit (IC) design with design-for-manufacturing (DFM). The interface includes a decryption module embedded in an IC design tool; an encrypted DFM data provided to an IC designer authorized for utilizing the encrypted DFM data; and a private key provided to the IC designer for decrypting the encrypted DFM data in the IC design tool.

Abstract translation: 用于制造设计（DFM）的集成电路（IC）设计的加密和解密接口。 该接口包括嵌入在IC设计工具中的解密模块; 提供给被授权使用加密的DFM数据的IC设计的加密的DFM数据; 以及提供给IC设计者的用于解密IC设计工具中加密的DFM数据的私钥。