公开(公告)号：US20100141324A1

公开(公告)日：2010-06-10

申请号：US12330768

申请日：2008-12-09

Applicant: Chua-Chin Wang ,  Tzung-Je Lee ,  Yi-Cheng Liu ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Tzung-Je Lee ,  Yi-Cheng Liu ,  Kuo-Chan Huang

IPC: H03L5/00

CPC classification number: H03K19/018521

Abstract: An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.

Abstract translation: 输出缓冲电路包括高电压检测电路，动态栅极偏置产生电路，输出级电路和焊盘电压检测器。 高电压检测电路检测电源电压，并根据电源电压产生第一和第二确定信号以及第一和第二偏置电压。 动态栅极偏置产生电路被第一和第二偏置电压偏置，并接收第一和第二确定信号，用于根据第一和第二确定信号将逻辑控制信号转换成相应的栅极偏置电压。 焊盘电压检测器检测I / O焊盘的电压，并为输出级电路提供焊盘电压检测信号，以修改输出到I / O焊盘的输出信号。 本文公开了混合电压输入/输出（I / O）缓冲器。

公开(公告)号：US20100097117A1

公开(公告)日：2010-04-22

申请号：US12289132

申请日：2008-10-21

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC: H03L5/00

CPC classification number: H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

Abstract: A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current.

Abstract translation: 混合电压输入/输出（I / O）缓冲器包括输出缓冲电路。 输出缓冲电路包括输出级电路，栅极跟踪电路和浮动N阱电路。 输出级电路包括堆叠上拉P型晶体管和堆叠式下拉式N型晶体管，其中堆叠上拉P型晶体管的第一P型晶体管和第一N型晶体管 堆叠的下拉式N型晶体管耦合到I / O焊盘。 栅极跟踪电路根据I / O焊盘的电压来控制第一P型晶体管的栅极电压，以防止漏电流。 浮动N阱电路为第一P型晶体管的N阱和第二P型晶体管的N阱提供N阱电压，控制栅极的第一P型晶体管的栅极电压 跟踪电路，以防止漏电流。

公开(公告)号：US07602324B1

公开(公告)日：2009-10-13

申请号：US12356107

申请日：2009-01-20

Applicant: Chih-Haur Huang ,  Kuo-Chan Huang

Inventor： Chih-Haur Huang ,  Kuo-Chan Huang

IPC: H03M1/20

CPC classification number: H03M1/0641 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/44

Abstract: A method for converting analog signals into digital signals includes the steps of: superimposing a dither value on an analog input signal; sampling the superimposition of the analog input signal with the dither value to obtain a sampling signal; converting the sampling signal into corresponding digital values; correcting offsets in the digital values to generate a digital signal; and removing the dither value from the digital signal. An analog-to-digital converter is also disclosed herein.

Abstract translation: 一种将模拟信号转换为数字信号的方法包括以下步骤：将抖动值叠加在模拟输入信号上; 对模拟输入信号与抖动值的叠加进行取样以获得采样信号; 将采样信号转换成相应的数字值; 校正数字值中的偏移量以产生数字信号; 并从数字信号中去除抖动值。 本文还公开了一种模拟 - 数字转换器。

公开(公告)号：US20090066367A1

公开(公告)日：2009-03-12

申请号：US12184271

申请日：2008-08-01

Applicant: Chua-Chin Wang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

Inventor： Chua-Chin Wang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

IPC: H03K19/0175

CPC classification number: H03K19/00315

Abstract: An input output device coupled between a core circuit and a pad and including an output cell, an input cell, and a pre-driver. The output cell includes an output stage and a voltage level converter. The output stage includes a first transistor and a second transistor connected to the first transistor in serial between a first supply voltage and a second voltage. The voltage level converter generates a first gate voltage to the first transistor according to the first voltage and a data signal. When the first supply voltage is increased, the first gate voltage is increased. When the data signal is at a high level, the first transistor is turned on. The input cell includes a pull unit and a first N-type transistor. The pre-driver turns off the first and the second transistors.

Abstract translation: 耦合在核心电路和焊盘之间并包括输出单元，输入单元和预驱动器的输入输出设备。 输出单元包括输出级和电压电平转换器。 输出级包括在第一电源电压和第二电压之间串联连接到第一晶体管的第一晶体管和第二晶体管。 电压电平转换器根据第一电压和数据信号产生到第一晶体管的第一栅极电压。 当第一电源电压增加时，第一栅极电压增加。 当数据信号处于高电平时，第一晶体管导通。 输入单元包括拉单元和第一N型晶体管。 预驱动器关闭第一和第二晶体管。

公开(公告)号：US20070103208A1

公开(公告)日：2007-05-10

申请号：US11594774

申请日：2006-11-09

Applicant: Kuo-Chan Huang ,  Chih-Haur Huang

Inventor： Kuo-Chan Huang ,  Chih-Haur Huang

IPC: H03B1/00

CPC classification number: H03F3/217 ,  G09G2310/0275 ,  G09G2320/0252 ,  G09G2330/021 ,  G09G2330/028 ,  H03F2200/78

Abstract: A buffer circuit applied to a source driver output stage circuit includes a buffer and a D-class amplifier. The buffer is coupled to an input voltage for accordingly outputting an output voltage. The D-class amplifier includes a comparator and a switch device. The comparator is for comparing the input voltage and the output voltage and accordingly outputting a comparison signal. The switch device is coupled to an operational voltage for adjusting the output voltage according to the comparison signal.

Abstract translation: 应用于源极驱动器输出级电路的缓冲电路包括缓冲器和D级放大器。 缓冲器耦合到输入电压，从而相应地输出输出电压。 D级放大器包括比较器和开关装置。 比较器用于比较输入电压和输出电压，从而输出比较信号。 开关装置耦合到用于根据比较信号调节输出电压的工作电压。

公开(公告)号：US20060170392A1

公开(公告)日：2006-08-03

申请号：US11043982

申请日：2005-01-28

Applicant: Kuo-Chan Huang ,  Hui-Chang Chuang

Inventor： Kuo-Chan Huang ,  Hui-Chang Chuang

IPC: H02J7/00

CPC classification number: H02J7/0054 ,  H02J7/0029 ,  H02J2007/006

Abstract: A portable charging system capable of improving the traditional charging structure and technology uses a programmable function and a controller memory method in a charging and discharging system, which can simultaneously charge and discharge the charger of a mobile electronic device or the charger of the charging system itself, or continue supplying the existing battery power in the original circuit to a mobile electronic device. The portable charging system has a mobile electronic device charging output port, a power input port, a program update input port, a chargeable/dischargeable battery, and a main system printed circuit board. The foregoing mobile electronic device charging output port, power input port and program update input port has the following circuit modules: a charging/discharging interface module, a charging module, a discharging module, a battery control interface module and a control module.

Abstract translation: 能够改善传统充电结构和技术的便携式充电系统在充电和放电系统中使用可编程功能和控制器存储方法，其可以同时对移动电子设备的充电器或充电系统本身的充电器进行充电和放电 ，或者继续将原始电路中的现有电池电力提供给移动电子设备。 便携式充电系统具有移动电子装置充电输出端口，电源输入端口，程序更新输入端口，可充电/可放电电池和主系统印刷电路板。 上述移动电子设备充电输出端口，电源输入端口和程序更新输入端口具有以下电路模块：充电/放电接口模块，充电模块，放电模块，电池控制接口模块和控制模块。